Display substrate, preparation method thereof, and display panel

Patent metadata

Field	Value
Publication number	US-12057457-B2
Application number	US-202017418218-A
Country	US
Kind code	B2
Filing date	Dec 29, 2020
Priority date	Mar 5, 2020
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

The present disclosure relates to the field of display technology, and discloses a display substrate, a preparation method thereof, and a display panel, used for improving the structure of the display substrate, improving characteristics of a thin film transistor, and increasing the yield of a display product. The display substrate includes: a base substrate; a thin film transistor on the base substrate; and a flattening layer on a side, away from the base substrate, of the thin film transistor, wherein the flattening layer is provided with a groove around a channel area of the thin film transistor, and an orthographic projection of the groove on the base substrate is not overlapped with an orthographic projection of the channel area on the base substrate.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate;
a thin film transistor on the base substrate;
a flattening layer on a side, away from the base substrate, of the thin film transistor, provided with a groove around a channel area of the thin film transistor, wherein an orthographic projection of the groove on the base substrate is not overlapped with an orthographic projection of the channel area on the base substrate;
a first electrode layer on a side, away from the base substrate, of the flattening layer, wherein the first electrode layer comprises a first portion in the groove, and the first portion covers a bottom of the groove and exposes a side wall of the groove; and
a first inorganic insulating layer on a side, away from the base substrate, of the first electrode layer, wherein the first inorganic insulating layer covers the bottom and the side wall of the groove.

2. The display substrate according to claim 1 , wherein the groove is an annular groove surrounding the channel area.

3. The display substrate according to claim 2 , wherein the groove comprises an annular body portion and a plurality of protruding portions protruding relative to a side wall of the annular body portion, and an orthographic projection of the protruding portions on the base substrate is on a side, facing the orthographic projection of the channel area on the base substrate, of an orthographic projection of the annular body portion on the base substrate.

4. The display substrate according to claim 2 , wherein the thin film transistor comprises source and drain electrodes, and the flattening layer further comprises a first via hole for exposing the source and drain electrodes;
the groove communicates with the first via hole; and a size of the first via hole is larger than a width of the groove.

5. The display substrate according to claim 2 , wherein a width of the groove is 1μm to 3μm.

6. The display substrate according to claim 1 , wherein the groove comprises a plurality of sections of groove bodies which surround the channel area and are sequentially arranged at intervals, and the plurality of sections of groove bodies are sequentially adjacent end to end without connecting with each other.

7. The display substrate according to claim 1 , wherein the groove is a blind groove with a depth smaller than a thickness of the flattening layer.

8. The display substrate according to claim 1 , wherein the groove is a through groove penetrating through the flattening layer in a thickness direction of the flattening layer.

9. The display substrate according to claim 1 , wherein an angle of gradient of the side wall of the groove is larger than 80 degrees.

10. A display panel, comprising the display substrate according to claim 1 , wherein the groove is in a non-open area of the display panel.

11. A preparation method of a display substrate, comprising:
preparing a thin film transistor on a base substrate;
preparing a flattening layer on the thin film transistor, wherein the flattening layer is provided with a groove around a channel area of the thin film transistor, and an orthographic projection of the groove on the base substrate is not overlapped with an orthographic projection of the channel area on the base substrate;
preparing a first electrode layer on the flattening layer, wherein the first electrode layer comprises a first portion in the groove, and the first portion covers a bottom of the groove and exposes a side wall of the groove; and
preparing a first inorganic insulating layer on the first electrode layer, wherein the first inorganic insulating layer covers the bottom and the side wall of the groove.

12. The preparation method according to claim 11 , wherein the preparing the flattening layer on the thin film transistor comprises:
coating the thin film transistor with an organic resin layer;
forming the groove, surrounding the channel area of the thin film transistor, in the organic resin layer through an exposure and development process, wherein a ratio of a depth of the groove to a thickness of the organic resin layer is larger than 1/2, the groove is annular and is a blind groove; and
treating the organic resin layer through an ashing process to cause the blind groove to become a through groove penetrating through the organic resin layer in a thickness direction of the organic resin layer.

13. The preparation method according to claim 12 , wherein the preparing the thin film transistor on the base substrate comprises:
sequentially preparing an active layer and source and drain electrodes on the base substrate; and
the preparing the flattening layer on the thin film transistor, further comprises:
forming the blind groove in the organic resin layer through the exposure and development process, and meanwhile forming a first via hole, for exposing the source and drain electrodes, in the organic resin layer, wherein a ratio of a width of the blind groove to a size of the first via hole ranges from 1/10 to 1/2.

14. The preparation method according to claim 12 , wherein the treating the organic resin layer through the ashing process comprises:
etching the organic resin layer by plasma etching equipment through bombardment with O 2 as working gas, so that organic resin layer residues at a bottom of the blind groove are removed.

15. The preparation method according to claim 11 , wherein the preparing the first electrode layer on the flattening layer comprises:
preparing the first electrode layer on the flattening layer through magnetron sputtering.

16. The preparation method according to claim 11 , wherein the preparing the first inorganic insulating layer on the first electrode layer comprises:
preparing the first inorganic insulating layer on the first electrode layer through a plasma enhanced chemical vapor deposition (PECVD) mode.

Assignees

• Hefei Boe Optoelectronics Tech
• Boe Technology Group Co Ltd

Inventors

• Gong Kui
• Duan Xianxue
• Cui Haifeng
• Liu Tianzhen
• Zhang Zhihai

Classifications

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/451 Primary

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title