Display device

Patent metadata

Field	Value
Publication number	US-12057045-B2
Application number	US-202318139054-A
Country	US
Kind code	B2
Filing date	Apr 25, 2023
Priority date	Jun 16, 2020
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

Provided is a display panel. The display panel includes multiple scanning lines, a gate driver circuit, and a timing controller. The timing controller is configured to: receive multiple data enable signals, generate a gate control signal, and provide the gate control signal for the gate driver circuit. The gate control signal includes a start signal, a first clock signal and a second clock signal. The multiple data enable signals are only within the active cycle. The timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval formed by a rising edge and a falling edge of a first data enable signal in the N th frame cycle.

First claim

What is claimed is:

1. A display device, comprising:
a plurality of scanning lines; a gate driver circuit electrically connected to the plurality of scanning lines; and a timing controller electrically connected to the gate driver circuit; wherein the timing controller is configured to: receive a plurality of data enable signals within each frame cycle of a plurality of frame cycles, generate a gate control signal according to the plurality of data enable signals, and provide the gate control signal for the gate driver circuit;
wherein the gate driver circuit is configured to provide scanning signals for the plurality of scanning lines according to the gate control signal;
wherein the gate control signal comprises a start signal, a first clock signal and a second clock signal;
wherein each frame cycle comprises an active cycle and a vertical blanking cycle, and the plurality of data enable signals are only within the active cycle;
wherein the timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval defined by a rising edge and a falling edge of a first data enable signal in an Nth frame cycle;
wherein N≥2; and
wherein when the timing controller is configured to generate the rising edge and the falling edge of the start signal within the time interval defined by the rising edge and the falling edge of the first data enable signal in the Nth frame cycle, a width of the first clock signal generated within the time interval defined by the rising edge and the falling edge of the first data enable signal in the Nth frame cycle is less than a width of the first clock signal generated outside the time interval defined by the rising edge and the falling edge of the first data enable signal in the Nth frame cycle, and a width of the second clock signal generated within the time interval defined by the rising edge and the falling edge of the first data enable signal in the Nth frame cycle is less than a width of the second clock signal generated outside the time interval defined by the rising edge and the falling edge of the first data enable signal in the Nth frame cycle.

2. The display device of claim 1 , wherein when the timing controller is configured to generate the rising edge and the falling edge of the start signal within the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle, the rising edge of the start signal is generated when the rising edge of the first data enable signal in the N th frame cycle is generated.

3. The display device of claim 1 , wherein when the timing controller is configured to generate the rising edge and the falling edge of the start signal within the time interval defined by the rising edge and the falling edge of the first data enable signal in the Nth frame cycle, a rising edge and a falling edge of the first clock signal are generated within the time interval defined by the rising edge and the falling edge of the first data enable signal in the Nth frame cycle.

4. The display device of claim 3 , wherein within the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle, the rising edge of the first clock signal is generated after a falling edge of the second clock signal.

5. The display device of claim 1 , wherein when the timing controller is configured to generate the rising edge and the falling edge of the start signal within the time interval defined by the rising edge and the falling edge of the first data enable signal in the Nth frame cycle, within the time interval defined by the rising edge and the falling edge of the first data enable signal in the Nth frame cycle, the falling edge of the start signal is generated when a rising edge of the first clock signal is generated.

6. The display device of claim 1 , wherein the gate driver circuit comprises a start signal line for transmitting the start signal, a first clock signal line for transmitting the first clock signal, a second clock signal line for transmitting the second clock signal, and a plurality of cascaded shift registers; wherein a shift register at each stage among the plurality of shift registers comprises a shift input terminal, an output terminal, a first signal terminal, a second signal terminal and a cascade signal terminal; wherein the plurality of shift registers comprise a first dummy shift register and a first-stage scanning shift register to an Mth-stage scanning shift register, wherein the first-stage scanning shift register and the first dummy shift register are cascaded, and M≥2;
wherein first signal terminals of scanning shift registers at even stages and the first dummy shift register are connected to the second clock signal line, and wherein the second signal terminals of the scanning shift registers at the even stages and the first dummy shift register are connected to the first clock signal line;
wherein first signal terminals of scanning shift registers at odd stages are connected to the first clock signal line, and wherein second signal terminals of the scanning shift registers at the odd stages are connected to the second clock signal line; and
wherein the shift input terminal of the first dummy shift register is connected to the start signal line, and the shift input terminal of a scanning shift register at each stage is connected to the cascade signal terminal of a scanning shift register at an upper stage of the scanning shift register at the each stage.

7. A display device, comprising:
a plurality of scanning lines; a gate driver circuit electrically connected to the plurality of scanning lines; and a timing controller electrically connected to the gate driver circuit; wherein the timing controller is configured to: receive a plurality of data enable signals within each frame cycle of a plurality of frame cycles, generate a gate control signal according to the plurality of data enable signals, and provide the gate control signal for the gate driver circuit;
wherein the gate driver circuit is configured to provide scanning signals for the plurality of scanning lines according to the gate control signal;
wherein the gate control signal comprises a start signal, a first clock signal and a second clock signal;
wherein each frame cycle comprises an active cycle and a vertical blanking cycle, and the plurality of data enable signals are only within the active cycle;
wherein the timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval defined by a rising edge and a falling edge of a first data enable signal in an Nth frame cycle;
wherein N≥2; and
wherein a rising edge and a falling edge of the second clock signal are generated within a time interval defined by the rising edge and the falling edge of the start signal.

8. The display device of claim 7 , wherein when the timing controller is configured to generate the rising edge and the falling edge of the start signal within the time interval defined by the rising edge and the falling edge of the first data enable signal in the N th frame cycle, the rising edge of the start signal is generated when the rising edge of the first data enable signal in the N th frame cycle is generated.

9. The display device of claim 7 , wherein when the timing controller is configured to generate the rising edge and the falling edge of the start signal within the time interval defined by the rising edge and the falling edge of the first data enable signal in the Nth frame cycle, a rising edge and a falling edge of the first clock signal are generated within the time interval defined by the rising edge and the falling edge of the first data

Assignees

• Xiamen Tianma Micro Electronics Co Ltd

Inventors

• Luo Sijian
• Wu Changzhi
• Xu Yumin

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0243

  Details of the generation of driving signals · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G2310/062

  Waveforms for resetting a plurality of scan lines at a time · CPC title