Wafer-tilt determination for slice-and-image process

Patent metadata

Field	Value
Publication number	US-12056865-B2
Application number	US-202117496345-A
Country	US
Kind code	B2
Filing date	Oct 7, 2021
Priority date	Oct 7, 2021
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

A dual-beam device, such as, a scanning electron microscope combined with a focused-ion beam milling column, is employed for a slice-in-image process. Based on one or more images of at least one cross-section of a test volume of a wafer, a wafer tilt is determined.

First claim

What is claimed is:

1. A method of operating a dual-beam device which comprises an imaging column, a particle detector and a milling column, the method comprising:
capturing at least one image of a test volume of a wafer mounted on a sample stage of the dual-beam device by operating the imaging column and the particle detector, the image depicting at least one cross-section of the test volume at at least one stage tilt of the sample stage, the at least one cross-section of the test volume obtained by slanted milling of the wafer using the milling column of the dual-beam device; and
determining at least one component of a wafer tilt of the wafer with respect to the sample stage taking into account knowledge of at least one structure of the wafer and the at least one image of the test volume of the wafer.

2. The method of claim 1 , wherein:
the at least one structure of the wafer comprises at least one semiconductor device structure of the wafer; and
the knowledge of the at least one structure of the wafer comprises a size of the at least one semiconductor device structure.

3. The method of claim 2 , wherein:
the size of the at least one semiconductor device structure comprises a depth offset between multiple layers of the semiconductor device; and
determining the at least one component of the wafer tilt comprises taking into account an imaged distance between the multiple layers of the semiconductor device in each image and taking into account the depth offset between the multiple layers of the semiconductor device.

4. The method of claim 3 , further comprising:
determining two orthogonal imaged distances between the multiple layers of the semiconductor device in each image; and
determining two orthogonal components of the wafer tilt by taking into account the two orthogonal imaged distances between the multiple layers of the semiconductor device layers in each image.

5. The method of claim 1 , wherein the at least one structure comprises at least one layer of the wafer, and the knowledge of the at least one structure of the wafer comprises a planarity of the at least one layer.

6. The method of claim 5 , wherein:
the at least one image comprises multiple images depicting a single cross-section of the test volume at multiple stage tilts of the sample stage; and
the method further comprises, for each one of the multiple images:
detecting at least one edge of the at least one layer of the wafer in a respective image; and
determining at least one component of the wafer tilt of the wafer taking into account a change of an appearance of the at least one edge between the multiple images and prior knowledge of the multiple stage tilts.

7. The method of claim 6 , wherein:
the at least one layer comprises multiple layers; and
the method further comprises for each one of the multiple images:
determining an imaged distance between adjacent edges of different ones of the multiple layers in the respective image; and
determining the at least one component of the wafer tilt by taking into account the change of the imaged distance between the multiple images.

8. The method of claim 7 , further comprising, for each one of the multiple images:
determining two orthogonal imaged distances between adjacent edges of different ones of the multiple layers in the respective image; and
determining two orthogonal components of the wafer tilt by taking into account the change of each one of the two orthogonal imaged distances between the multiple images.

9. The method of claim 6 , further comprising, for each one of the multiple images:
determining an image orientation of the at least one edge; and
determining the wafer tilt taking into account the change of the image orientation between the multiple images.

10. The method of claim 6 , wherein the at least one edge comprises a cutting edge of a slanted milling with respect to a top surface of the wafer.

11. The method of claim 6 , wherein the at least one edge comprises a cross-sectional edge of a slanted milling with respect to a semiconductor device layer of the wafer.

12. The method of claim 5 , wherein:
the at least one image comprises multiple images depicting multiple cross-sections obtained by the slanted milling at multiple milling depths and a single stage tilt; and
the method further comprises:
determining at least one offset between imaged positions of the at least one layer between the multiple images; and
determining the at least one component of the wafer tilt taking into account prior knowledge of the multiple milling depths and the at least one offset.

13. The method of claim 12 , further comprising:
obtaining at least one image for a first rotation of the sample stage with respect to the imaging column;
obtaining multiple further images of the test volume of the wafer mounted on the sample stage of the dual-beam device, the multiple further images being acquired using the imaging column and the particle detector, the multiple further images depicting multiple further cross sections of the test volume obtained by slanted milling at multiple further milling depths using the milling column, the multiple further images being obtained for a second rotation of the sample stage with respect to the imaging column, the first rotation being different from the second rotation;
determining at least one further offset between a further imaged position of the at least one layer of the wafer between the multiple further images; and
taking into account prior knowledge of the multiple further milling depths and the at least one further offset, determining a further component of the wafer tilt.

14. The method of claim 1 , wherein a milling angle between a milling axis of the slanted milling and a surface of the wafer is between 8° and 45°.

15. The method of claim 1 , further comprising:
controlling the imaging column and the particle detector to capture the at least one image of the test volume of the wafer; and
determining the at least one component of the wafer tilt of the wafer by operating a computer.

16. The method of claim 1 , further comprising reconstructing 3-D tomographic images of the test volume of the wafer taking into account the at least one component of the wafer tilt.

17. The method of claim 1 , further comprising changing the at least one stage tilt of the sample stage to compensate the determined at least one component of the wafer tilt.

18. The method of claim 1 , wherein:
the test volume of the wafer comprises at least one semiconductor device structure; and
the method further comprises determining, based on the determined at least one component of the wafer tilt, at least one member selected from the group consisting of (i) a tilt of the at least one semiconductor device structure with respect to a normal vector of the wafer, (ii) a three-dimensional shape of the at least one semiconductor device structure, or (iii) an orientation of the at least one semiconductor device structure in three dimensions.

19. The method of claim 18 , wherein the at least one semiconductor device structure comprise at least one vertical memory channel of a three-dimensional memory structure.

20. The method of claim 1 , wherein capturing the at least one image of the test volume of the wafer mounted on the sample stage of the dual-beam device by operating the imaging column and the particle detector comprises:
scanning a cross-section of a surface of the wafer with a beam of charged particles emitted by the imaging column, thereby generating sec

Assignees

• Zeiss Carl Smt Gmbh

Inventors

• Klochkov Dmitry
• Huynh Chuong
• Korb Thomas

Classifications

• G06T2207/30148

  Semiconductor; IC; Wafer · CPC title

• G06T2207/10072

  Tomographic images · CPC title

• G05B15/02

  electric · CPC title

• G06T7/13

  Edge detection · CPC title

• H01J2237/31745

  for preparing specimen to be viewed in microscopes or analyzed in microanalysers · CPC title