Methods and apparatus for repetitive histogramming

Patent metadata

Field	Value
Publication number	US-12055665-B2
Application number	US-202218069528-A
Country	US
Kind code	B2
Filing date	Dec 21, 2022
Priority date	Feb 19, 2020
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

Various embodiments of the present technology may provide methods and apparatus for repetitive histogramming. The apparatus may provide a limited number of physical bins to perform multiple histograms on a total number of virtual bins. The apparatus may provide a single physical bin that is used to sweep over the total number of virtual bins.

First claim

The invention claimed is:

1. A processor comprising:
memory that comprises a first plurality of physical bins, wherein the processor is configured to:
receive a value from a time-to-digital converter; and
using at least the value from the time-to-digital converter, histogram a second plurality of virtual bins using the first plurality of physical bins, wherein the second plurality is greater than the first plurality.

2. The processor defined in claim 1 , wherein histogramming the second plurality of virtual bins using the first plurality of physical bins comprises histogramming sequential segments of the second plurality of virtual bins.

3. The processor defined in claim 2 , wherein histogramming sequential segments of the plurality number of virtual bins comprises repeatedly histogramming the first plurality of virtual bins using the first plurality of physical bins.

4. The processor defined in claim 1 , further comprising:
a state machine that includes the memory, wherein the state machine is configured to receive the value from the time-to-digital converter.

5. The processor defined in claim 4 , wherein the state machine is configured to:
receive a sample count value; and
receive a laser clock signal.

6. The processor defined in claim 4 , further comprising:
a bin range register that is configured to receive a clock signal and a reset signal from the state machine.

7. The processor defined in claim 6 , further comprising:
an in-range detector that is configured to receive a range of values from the bin range register and the value from the time-to-digital converter, wherein the in-range detector is configured to determine if the value from the time-to-digital converter falls within the range of values.

8. The processor defined in claim 7 , further comprising:
an AND logic gate that is configured to receive an output from the in-range detector and the value from the time-to-digital converter, wherein the AND logic gate is configured to transmit an output to the state machine.

9. The processor defined in claim 4 , further comprising:
a peak latch that receives data from the state machine; and
a comparator configured to compare a first value from the state machine to a second value from the peak latch.

10. The processor defined in claim 9 , further comprising:
an AND logic gate that receives an output from the comparator and a clock signal.

11. The processor defined in claim 10 , further comprising:
a result latch that receives the value from the time-to-digital converter and an output from the AND logic gate, wherein the result latch is configured to output a peak result that indicates a virtual bin of the second plurality of virtual bins with a highest count value.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Buckley Steven John

Classifications

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• G01S17/10

  using transmission of interrupted, pulse-modulated waves (determination of distance by phase measurements G01S17/32) · CPC title

• G01S7/4865

  Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak (peak detection in noise, signal conditioning G01S7/487) · CPC title

• G01S17/14

  wherein a voltage or current pulse is initiated and terminated in accordance with the pulse transmission and echo reception respectively, e.g. using counters · CPC title

• G01S7/4861 Primary

  Circuits for detection, sampling, integration or read-out · CPC title