Integrated test circuit, test assembly and method for testing an integrated circuit

Patent metadata

Field	Value
Publication number	US-12055587-B2
Application number	US-202217947495-A
Country	US
Kind code	B2
Filing date	Sep 19, 2022
Priority date	Oct 29, 2021
Publication date	Aug 6, 2024
Grant date	Aug 6, 2024

Abstract

An integrated circuit includes a ring oscillator circuit and a plurality of logic paths. Each logic path comprises a path input connection, a path output connection and an input multiplexer, which has an output connection that is connected to the path input connection of the logic path. Each logic path, beginning with a first logic path, is assigned a respective subsequent logic path by virtue of the path output connection of the logic path being connected to a data input connection of the input multiplexer of the subsequent logic path. A last logic path of the logic paths is assigned the first logic path as subsequent logic path. For each logic path, the multiplexer is configured such that, when a control signal that indicates a test mode is fed thereto, it connects the data input connection of the input multiplexer to the path input connection of the logic path.

First claim

What is claimed is:

1. An integrated circuit, comprising:
at least one ring oscillator circuit, comprising:
a plurality of logic paths, wherein each logic path comprises a path input connection, a path output connection and an input multiplexer, which has an output connection that is connected to the path input connection of the logic path,
wherein a first logic path of the plurality of logic paths has a path output connection connected to a data input connection of the input multiplexer of a subsequent logic path, and wherein the subsequent logic path has a path output connection connected to a data input connection of the input multiplexer of a last logic path of the plurality of logic paths, and wherein the last logic path has a path output connection connected to a data input connection of the input multiplexer of the first logic path; and
wherein, for each logic path, the input multiplexer is configured such that, when a control signal that indicates a test mode is fed thereto, the input multiplexer connects the data input connection of the input multiplexer to the path input connection of the logic path.

2. The integrated circuit as claimed in claim 1 , wherein each logic path comprises a chain of a plurality of logic gates connected one behind the other and/or comprises a data bus line.

3. The integrated circuit of claim 1 , wherein the input multiplexer comprises another data input connection configured such that, when a control signal that indicates a normal operating mode is fed thereto, the input multiplexer connects the other data input connection to the path input connection of the logic path.

4. The integrated circuit of claim 1 , wherein the input multiplexer is a 2-to-1 multiplexer.

5. The integrated circuit of claim 1 , wherein the at least one ring oscillator circuit comprises a test output connection and the integrated circuit comprises a test terminal to which the test output connection is connected.

6. The integrated circuit of claim 5 , wherein the test output connection is arranged at a link between one of the logic paths and the subsequent logic path.

7. The integrated circuit of claim 1 ,
wherein each logic path of the plurality of logic paths comprises a chain of a plurality of logic gates connected in series with one other and wherein the at least one ring oscillator circuit is assigned to one or more scan flip-flops, which are connected to input connections of at least a portion of the logic gates of the chains of logic gates of the ring oscillator circuit and are configured such that, when the one or more scan flip-flops store a predefined side input pattern, for each logic path of the ring oscillator circuit, the logic gates of the chain of the logic path form a serial 1-bit logic path from an input connection of a first logic gate of the chain of the logic path to the output connection of a last logic gate of the chain of the logic path.

8. The integrated circuit of claim 1 , wherein each logic path is assigned a scan flip-flop group, which contains at least one scan flip-flop, wherein at least one scan flip-flop of the scan flip-flop group is connected to a second data input connection of the input multiplexer of the logic path.

9. The integrated circuit of claim 1 , comprising a multiplicity of ring oscillator circuits, wherein each ring oscillator circuit comprises:
a plurality of logic paths, wherein each logic path comprises a path input connection, a path output connection and an input multiplexer, which has an output connection that is connected to the path input connection of the logic path,
wherein a first logic path of the plurality of logic paths has a path output connection connected to a data input connection of the input multiplexer of a subsequent logic path, and wherein the subsequent logic path has a path output connection connected to a data input connection of the input multiplexer of a last logic path of the plurality of logic paths, and wherein the last logic path has a path output connection connected to a data input connection of the input multiplexer of the first logic path;
wherein, for each logic path, the input multiplexer is configured such that, when a control signal that indicates a test mode is fed thereto, the input multiplexer connects the data input connection of the input multiplexer to the path input connection of the logic path.

10. The integrated circuit as claimed in claim 9 , wherein each logic path of each ring oscillator circuit is assigned a scan flip-flop group, which contains at least one scan flip-flop, wherein the at least one scan flip-flop of the scan flip-flop group is connected to a second data input connection of the input multiplexer of the logic path, wherein the logic paths of different ring oscillator circuits are assigned different scan flip-flop groups.

11. A test assembly for testing the integrated circuit of claim 10 , which is configured, for each ring oscillator circuit and each logic path, to feed the control signal that indicates the test mode to the input multiplexer of the logic path of the ring oscillator circuit and to receive measurement signals generated by the ring oscillator circuits in the test mode.

12. The test assembly as claimed in claim 11 , comprising an analysis device configured to ascertain a performance of the integrated circuit from oscillation frequencies of the measurement signals received.

13. A method for testing the integrated circuit of claim 10 , comprising:
for each ring oscillator circuit and each logic path, feeding the control signal that indicates the test mode to the input multiplexer of the logic path of the ring oscillator circuit, and
receiving measurement signals generated by the ring oscillator circuits in the test mode.

14. An integrated circuit, comprising:
a first multiplexer comprising a first first multiplexer input, a second first multiplexer input, a first multiplexer output, and a first multiplexer control;
a first logic path comprising a first logic path input and a first logic path output, the first logic path input coupled to the first multiplexer output;
a second multiplexer comprising first second multiplexer input, a second second multiplexer input, a second multiplexer output, and a second multiplexer control, the second multiplexer control coupled to the first multiplexer control and the first second multiplexer input coupled to the first logic path output;
a second logic path comprising a second logic path input and a second logic path output, the second logic path input coupled to the second multiplexer output and the second logic path output coupled to the second first multiplexer input;
a first input scan flip-flop comprising a first input scan flip-flop input and a first input scan flip-flop output, the first input scan flip-flop output coupled to the first first multiplexer input; and
a second input scan flip-flop comprising a second input scan flip-flop input and a second input scan flip-flop output, the second input scan flip-flop output coupled to the second second multiplexer input.

15. The integrated circuit of claim 14 :
wherein the first logic path comprises a first number of logic gates arranged in series with one another and having respective first side inputs by which the first number of logic gates can be configured as a first number of inverters; and
wherein the second logic path comprises a second number of logic gates arranged in series with one another and having respective second side inputs by which the second number of logic gates can be configured as a second number of inverters; and
wherein the first number plus the second number is

Assignees

• Infineon Technologies Ag

Inventors

• Kilian Tobias
• Huch Martin
• Ahrens Heiko
• Tille Daniel

Classifications

• G01R31/3016 Primary

  Delay or race condition test, e.g. race hazard test · CPC title

• G01R31/2856

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title

• G01R31/318594

  Timing aspects (clock circuits G01R31/318552) · CPC title

• H03K3/0315

  Ring oscillators · CPC title

• G01R31/31855

  Interconnection testing, e.g. crosstalk, shortcircuits · CPC title