Cyclic redundancy check (CRC) update mechanism

Patent metadata

Field	Value
Publication number	US-12052170-B2
Application number	US-202017020654-A
Country	US
Kind code	B2
Filing date	Sep 14, 2020
Priority date	Sep 25, 2015
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

A cyclic redundancy code (CRC) update device includes an input coupled to obtain an old CRC that corresponds to an old header of a communication packet, a CRC storage device to store CRC coefficients, a CRC calculator coupled to receive a modified old header of the communication packet and calculate a new CRC on the modified old header, and a polynomial multiplier coupled to the CRC storage device to receive the new CRC, obtain a corresponding coefficient from the CRC storage device, and generate an update for the CRC of the frame.

First claim

What is claimed is:

1. A method of updating a cyclic redundancy code (CRC) of a packet in an apparatus, the method comprising:
processing the packet as the packet traverses a datapath of the apparatus, the processing comprising:
determining whether a header of the packet has changed to a new header, wherein the packet includes a single CRC value and wherein the single CRC value is separate from the header of the packet; and
in response to a determination that the header has changed, modifying the packet by updating an existing value of the single CRC value to a new CRC value without using a contribution of a payload of the packet to the updating.

2. The method of claim 1 , wherein the processing further comprises:
calculating an existing contribution of the header to the existing value of the single CRC value; and
calculating a new contribution of the new header to the new CRC;
wherein the updating comprises replacing the existing contribution with the new contribution.

3. The method of claim 2 , wherein the processing further comprises, prior to updating the existing value of the single CRC value, advancing the existing value of the single CRC value by at least a number of bytes occurring after the header and advancing the new CRC by at least a number of bytes occurring after the new header.

4. The method of claim 3 , wherein if the packet contains multiple headers, at least one of which changes:
advancing the existing value of the single CRC value comprises advancing the existing value of the single CRC value by a number of bytes occurring after all headers of the packet prior to changing the header of the packet to the new header, and
advancing the new CRC comprises advancing the existing value of the single CRC value by a number of bytes occurring after all headers of the packet after changing the header of the packet to the new header.

5. The method of claim 4 , wherein the processing further comprises, for each of the headers:
determining whether the header has changed to a second header; and
in response to a determination that the header has changed to the second header, calculating a second contribution of the second header to the new CRC; and
the updating comprises replacing a first contribution with the second contribution if the header has changed and maintaining the first contribution if the header has not changed.

6. The method of claim 2 , wherein the processing further comprises compacting the packet having the new header after calculating the new contribution and prior to updating the existing value of the single CRC value.

7. The method of claim 6 , wherein:
a first latency is associated with calculating the existing contribution,
a second latency is associated with calculating the new contribution,
a sum of the first and second latency is shorter than a latency associated with changing the header to the new header and compacting the packet.

8. The method of claim 1 , wherein the processing further comprises, for updating of the existing value of the single CRC value, storing the payload of the packet without storing the header.

9. The method of claim 1 , wherein the processing further comprises:
parsing the packet and determining a routing modification of the packet; and
providing packet to a data plane interface of the apparatus.

10. The method of claim 1 , wherein the apparatus is a switch.

11. An apparatus comprising processing circuitry and memory,
wherein the processing circuitry is configured to:
determine whether a header of a packet traversing a datapath of the apparatus has changed to a new header, wherein the packet includes a single cyclic redundancy code (CRC) value; and
in response to a determination that the header has changed, modify the packet by updating an existing value of the single CRC value to a new CRC value without using a contribution of a payload of the packet to the updating, and the memory is configured to store the payload, the new header of the packet.

12. The apparatus of claim 11 , wherein the processing circuitry is further configured to:
calculate an existing contribution of the header to the existing value of the single CRC value; and
calculate a new contribution of the new header to the new CRC; and
update the CRC by replacing the existing contribution with the new contribution.

13. The apparatus of claim 12 , wherein the processing circuitry is further configured to, prior to updating the existing value of the single CRC value, advance the existing value of the single CRC value by at least a number of bytes occurring after the header and advance the new CRC by at least a number of bytes occurring after the new header.

14. The apparatus of claim 13 , wherein the processing circuitry is further configured to, if the packet contains multiple headers, at least one of which changes:
advance the existing value of the single CRC value by advancing the existing value of the single CRC value by a number of bytes occurring after all headers of the packet prior to changing the header of the packet to the new header, and
advance the new CRC by advancing the existing value of the single CRC value by a number of bytes occurring after all headers of the packet after changing the header of the packet to the new header.

15. The apparatus of claim 14 , wherein the processing circuitry is further configured to, for each of the headers:
determine whether the header has changed to a second header; and
in response to a determination that the header has changed to the second header, calculate a second contribution of the second header to the new CRC; and
update the CRC by replacing a first contribution with the second contribution if the header has changed and maintaining the first contribution if the header has not changed.

16. The apparatus of claim 12 , wherein the processing circuitry is further configured to compact the packet having the new header after calculating the new contribution and prior to updating the existing value of the single CRC value.

17. The apparatus of claim 16 , wherein:
a first latency is associated with calculating the existing contribution,
a second latency is associated with calculating the new contribution,
a sum of the first and second latency is shorter than a latency associated with changing the header to the new header and compacting the packet.

18. The apparatus of claim 11 , wherein the processing circuitry is further configured to, for update the existing value of the single CRC value, store the payload of the packet without storing the header.

19. The apparatus of claim 11 , wherein the processing circuitry is further configured to:
parse the packet and determine a routing modification of the packet; and
provide packet to a data plane interface of the apparatus.

20. The apparatus of claim 11 , wherein the apparatus is a switch.

21. The apparatus of claim 11 , wherein the determination that the header has changed is based on the header including multiple headers.

Assignees

• Intel Corp

Inventors

• Papadantonakis Karl S
• Southworth Robert G
• Gravel Alain
• Dama Jonathan A

Classifications

• H04L69/22

  Parsing or analysis of headers · CPC title

• H04L45/74 Primary

  Address processing for routing · CPC title

• H03M13/093 Primary

  CRC update after modification of the information word · CPC title