Scheduling of iterative decoding depending on soft inputs

Patent metadata

Field	Value
Publication number	US-12052033-B2
Application number	US-202217863425-A
Country	US
Kind code	B2
Filing date	Jul 13, 2022
Priority date	Jul 13, 2022
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

A decoder includes circuitry and multiple Variable-Node Circuits (VNCs). The VNCs individually hold one or more variables of an Error Correction Code (ECC) that is representable by a plurality of check equations defined over the variables. The circuitry is configured to receive a code word including variables having m-bit values that was encoded using the ECC, to further receive reliability levels assigned respectively to the variables, to decode the code word by applying to the code word a sequence of iterations, including deciding in a given iteration whether a given VNC is to be processed or skipped in that iteration, depending on the reliability levels assigned to the variables of the given VNC, and, when the given VNC is selected for processing, to make a decision whether or not to update one or more of the variables of the given VNC, and to apply the decision by the given VNC.

First claim

The invention claimed is:

1. A decoder, comprising:
multiple Variable-Node Circuits (VNCs), configured to individually hold one or more variables of an Error Correction Code (ECC) that is representable by a plurality of check equations defined over the variables, wherein a given VNC among the VNCs is associated with a plurality of the variables; and
logic circuitry, configured to:
receive for decoding a code word that was encoded using the ECC, the code word comprising multiple variables having m-bit values, m being a positive integer;
further receive multiple reliability levels assigned respectively to the variables of the received code word, wherein the reliability levels comprise predefined binary reliability values having a High Reliability (HR) value and a Low Reliability (LR) value;
decode the received code word by applying to the code word a sequence of iterations, including, in a given iteration in the sequence, holding for the given iteration predefined first and second skipping thresholds associated respectively with the LR and the HR values, evaluating a number of the variables associated with the given VNC that are assigned to the LR value, and deciding whether to skip or process the given VNC based on the first skipping threshold when the evaluated number is higher than a predefined threshold number, or based on the second skipping threshold when the evaluated number is lower than or equal to the predefined threshold number; and
when the given VNC is selected for processing, make a decision whether or not to update one or more of the values of the variables associated with the given VNC, and apply the decision by the given VNC.

2. The decoder according to claim 1 , wherein, prior to performing the sequence of iterations, the logic circuitry is configured to derive, based at least on the reliability levels, a schedule specifying which of the VNCs are to be processed and which of the VNCs are to be skipped in one or more of the iterations, and to decide to process or skip the VNCs during performing the iterations based on the derived schedule.

3. The decoder according to claim 1 , wherein the variables of the code word have binary values, and wherein the logic circuitry is configured to calculate a score value for a given variable of the given VNC, based at least on the reliability level assigned to the given variable, the score value being indicative of a confidence level of the given variable holding a correct binary value corresponding to a successfully decoded version of the code word, and to make the decision for the given variable based on the score value.

4. The decoder according to claim 3 , wherein the logic circuitry is configured to select a bit-flipping threshold from among multiple predefined bit-flipping thresholds associated respectively with the predefined reliability values, depending on the reliability level assigned to the given variable, and to make the decision to update the value of the given variable by flipping the binary value of the given variable when the score value calculated for the given variable exceeds the selected bit-flipping threshold.

5. The decoder according to claim 3 , wherein the logic circuitry is configured to calculate the score value for the given variable based on (i) a number of the check equations of the ECC in which the given variable participates and that are unsatisfied, (ii) an indication of whether the binary value of the given variable differs from a corresponding binary value in the received code word, and (iii) a predefined weight value applied to the indication, the weight value depending on the reliability level assigned to the given variable.

6. The decoder according to claim 1 , wherein the ECC comprising a Low-Density Parity-Check (LDPC) code, in which a parity-check matrix comprises multiple sub-matrices arranged in block-rows and block-columns, and wherein the plurality of the variables of the given VNC are (i) associated with a respective block-column of the parity-check matrix, and (ii) participate in a common number of check equations among the plurality of the check equations.

7. The decoder according to claim 1 , wherein the logic circuitry is configured to make the decision for at least two of the plurality of the variables associated with the given VNC, in parallel to one another.

8. The decoder according to claim 1 , wherein the circuitry is configured to decide that the given VNC is to be skipped in a subsequence of one or more initial iterations of the sequence of iterations.

9. A method for decoding, comprising:
in a decoder comprising multiple Variable-Node Circuits (VNCs) that individually hold one or more variables of an Error Correction Code (ECC) that is representable by a plurality of check equations defined over the variables, wherein a given VNC among the VNCs is associated with a plurality of the variables,
receiving for decoding a code word that was encoded using the ECC, the code word comprising multiple variables having m-bit values, m being a positive integer;
further receiving multiple reliability levels assigned respectively to the variables of the received code word, wherein values of the reliability levels comprise predefined binary reliability values having a High Reliability (HR) value and a Low Reliability (LR) value;
decoding the received code word by applying to the code word a sequence of iterations, including, in a given iteration in the sequence, holding for the given iteration predefined first and second skipping thresholds associated respectively with the LR and the HR values, evaluating a number of the variables associated with the given VNC that are assigned to the LR value, and deciding whether to skip or process the given VNC based on the first skipping threshold when the evaluated number is higher than a predefined threshold number, or based on the second skipping threshold when the evaluated number is lower than or equal to the predefined threshold number; and
when the given VNC is selected for processing, making a decision whether or not to update one or more of the values of the variables associated with the given VNC, and applying the decision by the given VNC.

10. The method according to claim 9 , and comprising, prior to performing the sequence of iterations, deriving, based at least on the reliability levels, a schedule specifying which of the VNCs are to be processed and which of the VNCs are to be skipped in one or more of the iterations, and deciding to process or skip the VNCs during performing the iterations based on the derived schedule.

11. The method according to claim 9 , wherein the variables of the code word have binary values, and comprising calculating a score value for a given variable of the given VNC, based at least on the reliability level assigned to the given variable, the score value being indicative of a confidence level of the given variable holding a correct binary value corresponding to a successfully decoded version of the code word, and making the decision for the given variable based on the score value.

12. The method according to claim 11 , wherein making the decision comprises selecting a bit-flipping threshold from among multiple predefined bit-flipping thresholds associated respectively with the predefined reliability values, depending on the reliability level assigned to the given variable, and making the decision to update the value of the given variable by flipping the binary value of the given variable when the score value calculated for the given variable exceeds the selected bit-flipping threshold.

13. The method according to claim 11 , wherein calculating the score value for the given variable comprises c

Assignees

• Apple Inc

Inventors

• Roth Roy
• Tate Yonathan

Classifications

• H03M13/015

  Simulation or testing of codes, e.g. bit error rate [BER] measurements · CPC title

• H03M13/1134

  Full parallel processing, i.e. all bit nodes or check nodes are processed in parallel · CPC title

• H03M13/1131 Primary

  Scheduling of bit node or check node processing · CPC title

• H03M13/1137

  Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel · CPC title

• H03M13/43

  Majority logic or threshold decoding · CPC title