Semiconductor epitaxy structure

Patent metadata

Field	Value
Publication number	US-12051724-B2
Application number	US-202217827805-A
Country	US
Kind code	B2
Filing date	May 30, 2022
Priority date	Oct 29, 2021
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

A semiconductor epitaxy structure includes a silicon carbide substrate, a nucleation layer, a gallium nitride buffer layer, and a stacked structure. The nucleation layer is formed on the silicon carbide substrate, the gallium nitride buffer layer is disposed on the nucleation layer, and the stacked structure is formed between the nucleation layer and the gallium nitride buffer layer. The stacked structure includes: a plurality of silicon nitride (SiN x ) layers and a plurality of aluminum gallium nitride (Al x Ga 1-x N) layers alternately stacked, wherein the first layer of the plurality of silicon nitride layers is in direct contact with the nucleation layer.

First claim

What is claimed is:

1. A semiconductor epitaxy structure, comprising:
a silicon carbide substrate;
a nucleation layer formed on the silicon carbide substrate;
a gallium nitride buffer layer disposed on the nucleation layer; and
a stacked structure formed between the nucleation layer and the gallium nitride buffer layer, and the stacked structure is formed by a plurality of superlattice (SLs) layers, each of the superlattice layers is formed by one of the silicon nitride layers and one of the aluminum gallium nitride layers, the aluminum gallium nitride layer is formed by a first aluminum gallium nitride thin film and a second aluminum gallium nitride thin film, and the first aluminum gallium nitride thin film is located between the second aluminum gallium nitride thin film and the silicon nitride layer, and an aluminum content of the first aluminum gallium nitride thin film is higher than an aluminum content of the second aluminum gallium nitride thin film.

2. The semiconductor epitaxy structure of claim 1 , wherein the stacked structure accounts for 40% to 60% of a total thickness of the semiconductor epitaxy structure.

3. The semiconductor epitaxy structure of claim 1 , wherein a ratio of a thickness of the first aluminum gallium nitride thin film to a thickness of the second aluminum gallium nitride thin film is 1:2 to 1:10.

4. The semiconductor epitaxy structure of claim 1 , wherein a thickness of each of the superlattice layers is between 20 nm and 50 nm.

5. The semiconductor epitaxy structure of claim 1 , wherein a thickness of the silicon nitride layer in the superlattice layers is between 1 nm and 20 nm.

6. The semiconductor epitaxy structure of claim 1 , wherein the nucleation layer is an aluminum nitride (AlN) nucleation layer, and has a thickness between 1 nm and 100 nm.

7. The semiconductor epitaxy structure of claim 1 , wherein a thickness of the silicon carbide substrate is between 100 μm and 350 μm.

8. The semiconductor epitaxy structure of claim 1 , wherein a basal plane dislocation (BPD) density of the silicon carbide substrate is between 3000 cm −2 and 6000 cm −2 .

9. A semiconductor epitaxy structure, comprising:
a silicon carbide substrate;
a nucleation layer formed on the silicon carbide substrate;
a gallium nitride buffer layer disposed on the nucleation layer, wherein a material of the gallium nitride buffer layer comprises doped carbon gallium nitride (C:GaN) or doped iron gallium nitride (Fe:GaN); and
a stacked structure formed between the nucleation layer and the gallium nitride buffer layer, and the stacked structure comprises:
a plurality of silicon nitride (SiN x ) layers, wherein a first layer in the plurality of silicon nitride layers is in direct contact with the nucleation layer; and
a plurality of aluminum gallium nitride (Al x Ga 1-x N) layers, stacked alternately with the plurality of silicon nitride layers, wherein a topmost layer of the stacked structure is one of the aluminum gallium nitride layers which is in direct contact with the gallium nitride buffer layer.

10. The semiconductor epitaxy structure of claim 9 , wherein a thickness of each of the plurality of silicon nitride layers is gradually reduced toward the gallium nitride buffer layer.

Assignees

• Globalwafers Co Ltd

Inventors

• Lin Tzu-Yao
• Liu Jia-Zhe
• Shih Ying-Ru

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3238

  being insulating materials · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title