Chip card body, method for forming a chip card body and chip card

Patent metadata

Field	Value
Publication number	US-12051640-B2
Application number	US-202117498828-A
Country	US
Kind code	B2
Filing date	Oct 12, 2021
Priority date	Oct 13, 2020
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

A chip card body including a metal plate having at least one slot which defines a current flow path on the metal plate, and having a coupling region to accommodate a chip with an antenna, wherein the coupling region is configured to inductively couple the metal plate to the antenna of the chip, a dielectric layer applied to the metal plate, an electrically conductive layer applied to a side of the dielectric layer opposite the metal plate, and at least one electrically conductive coupling between the metal plate and the electrically conductive layer, wherein the metal plate, the dielectric layer and the electrically conductive layer form a capacitor.

First claim

The invention claimed is:

1. A chip card body, comprising:
a metal plate having at least one slot which defines a current flow path on the metal plate, and having a coupling region configured to accommodate a chip with an antenna, and configured to inductively couple the metal plate to the antenna of the chip;
a dielectric layer applied to the metal plate;
a first electrically conductive layer applied to a side of the dielectric layer opposite the metal plate, and comprising a main capacitor region and at least one tuning region,
wherein the at least one tuning region is connected to the main capacitor region only by means of a narrow connecting region so that the tuning region is separable from the main capacitor region by cutting through the narrow connecting region; and
at least one electrically conductive coupling between the metal plate and the first electrically conductive layer,
wherein the metal plate, the dielectric layer, and the first electrically conductive layer form a capacitor.

2. The chip card body as claimed in claim 1 ,
wherein the narrow connecting region has a width not exceeding one tenth of the circumference of the first electrically conductive layer.

3. The chip card body as claimed in claim 1 ,
wherein the first electrically conductive layer comprises at least one slot.

4. The chip card body as claimed in claim 3 ,
wherein the at least one slot of the first electrically conductive layer extends above the slot of the metal plate.

5. A chip card, comprising:
a chip card body as claimed in claim 1 ; and
a chip accommodated in the coupling region and having an antenna.

6. A chip card body, comprising:
a metal plate having at least one slot which defines a current flow path on the metal plate, and having a coupling region configured to receive a chip with an antenna, and configured to inductively couple the metal plate with the antenna of the chip;
a dielectric layer applied to the metal plate;
a first electrically conductive layer applied to a side of the dielectric layer opposite the metal plate;
a second dielectric layer on the first electrically conductive layer; and
a second electrically conductive layer on the second dielectric layer;
an electrically conductive coupling between the metal plate and the first electrically conductive layer; and
a second electrically conductive coupling between the metal plate and the second electrically conductive layer, and comprising a main capacitor region and at least one tuning region,
wherein the at least one tuning region is connected to the main capacitor region only by means of a narrow connecting region so that the tuning region can be separated from the main capacitor region by cutting through the narrow connecting region, and
wherein the first electrically conductive layer, the second dielectric layer, and the second electrically conductive layer form a capacitor.

7. The chip card body as claimed in claim 6 ,
wherein the narrow connecting region has a width not exceeding one tenth of the circumference of the second electrically conductive layer.

Assignees

• Infineon Technologies Ag

Inventors

• Pachler Walther
• Huber Michael
• Pohl Jens
• Tompa-Antal Szabolcs

Classifications

• H10W70/6875

  being on a metallic substrate, e.g. insulated metal substrates [IMS] · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title

• G06K19/07756

  the connection being non-galvanic, e.g. capacitive · CPC title