Methods for forming semiconductor structures and semiconductor structures

Patent metadata

Field	Value
Publication number	US-12051618-B2
Application number	US-202117430279-A
Country	US
Kind code	B2
Filing date	Feb 8, 2021
Priority date	Feb 27, 2020
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure and a semiconductor structure. The method for forming a semiconductor structure comprises: forming an interconnect layer and a conductive layer covered on a surface of the interconnect layer; forming a protective layer covering a surface of the conductive layer away from the interconnect layer; forming a trench penetrating the protective layer and the conductive layer; and filling a dielectric layer in the trench, and forming an air gap in the dielectric layer, the air gap extending from the trench in the conductive layer into the trench in the protective layer.

First claim

The invention claimed is:

1. A method for forming a semiconductor structure, comprising:
forming an interconnect layer and a conductive layer covering a surface of the interconnect layer;
forming a protective layer covering a surface of the conductive layer away from the interconnect layer;
forming a trench penetrating the protective layer and the conductive layer by an etching process, wherein chamfering caused by the etching process occurs only in the protective layer; and
filling a dielectric layer in the trench, and forming an air gap in the dielectric layer, the air gap extending from the trench in the conductive layer into the trench in the protective layer.

2. The method for forming a semiconductor structure according to claim 1 , wherein the interconnect layer comprises a plurality of interconnect lines and an isolation layer located between adjacent interconnect lines of the plurality of interconnect lines; and the forming an interconnect layer and a conductive layer covering a surface of the interconnect layer comprises:
forming a first adhesive layer on the surface of the interconnect layer; and
depositing a metal material on a surface of the first adhesive layer away from the interconnect layer, to form the conductive layer.

3. The method for forming a semiconductor structure according to claim 2 , wherein the forming a protective layer covering a surface of the conductive layer away from the interconnect layer comprises:
forming a second adhesive layer on the surface of the conductive layer away from the first adhesive layer; and
depositing a dielectric material on a surface of the second adhesive layer to form the protective layer.

4. The method for forming a semiconductor structure according to claim 3 , wherein the depositing a dielectric material on a surface of the second adhesive layer comprises:
depositing the dielectric material on the surface of the second adhesive layer by a plasma-enhanced chemical vapor deposition process or a high-density plasma chemical vapor deposition process.

5. The method for forming a semiconductor structure according to claim 3 , wherein the forming a trench penetrating the protective layer and the conductive layer comprises:
etching at least the protective layer, the second adhesive layer, the conductive layer and the first adhesive layer, to form the trench penetrating the protective layer, the second adhesive layer, the conductive layer and the first adhesive layer.

6. The method for forming a semiconductor structure according to claim 5 , wherein the forming a trench penetrating the protective layer and the conductive layer comprises:
etching the protective layer, the second adhesive layer, the conductive layer, the first adhesive layer and part of the isolation layer, to form the trench penetrating the protective layer, the second adhesive layer, the conductive layer and the first adhesive layer and extending into the isolation layer.

7. The method for forming a semiconductor structure according to claim 1 , wherein the protective layer is made of one or a combination of two or more of oxide materials, nitride materials and oxynitride materials.

8. The method for forming a semiconductor structure according to claim 1 , wherein the filling a dielectric layer in the trench comprises:
filling the dielectric layer in the trench by a high-density plasma deposition process.

9. The method for forming a semiconductor structure according to claim 1 , wherein a top surface of the air gap is flush with a top surface of the protective layer; or
the top surface of the air gap is below the top surface of the protective layer.

Assignees

• Changxin Memory Tech Inc

Inventors

• Yang Nianwang
• Wang Yuchen

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/072 Primary

  of dielectric parts comprising air gaps · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title