Read operations for active regions of a memory device

Patent metadata

Field	Value
Publication number	US-12050786-B2
Application number	US-202117628800-A
Country	US
Kind code	B2
Filing date	Mar 16, 2021
Priority date	Mar 16, 2021
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

Methods, systems, and devices for read operations for active regions of a memory device are described. A memory system that includes a non-volatile memory device may receive a command to enter a first power mode. Before entering the first power mode, the memory system may store an indication of the active regions of the non-volatile memory device that are active for use as part of a host performance booster (HPB) mode. The memory device may receive an HPB command while in the first power mode, and may subsequently enter (e.g., re-enter) the second power mode. In some examples, the HPB command may be processed based on its physical address being included in one of the active regions of the non-volatile memory device.

First claim

What is claimed is:

1. A memory system, comprising:
a non-volatile memory device;
a cache for storing a mapping between logical addresses and physical addresses of the non-volatile memory device; and
a controller coupled with the non-volatile memory device and the cache, wherein the controller is configured to cause the memory system to:
receive a command for entering a first power mode;
store an indication of an active region of the non-volatile memory device that is configured for use as part of a host performance booster mode based at least in part on receiving the command;
enter the first power mode based at least in part on storing the indication;
receive a read command that includes a physical address of the non- volatile memory device in the active region of the non-volatile memory device based at least in part on entering the first power mode;
transition to a second power mode from the first power mode based at least in part on receiving the read command;
and perform, while the non-volatile memory device is operating in the second power mode, a read operation using the physical address of the non-volatile memory device based at least in part on receiving the read command.

2. The memory system of claim 1 , wherein the controller is further configured to cause the memory system to:
loading, to the cache, the indication of the active region of the non-volatile memory device based at least in part on transitioning to the second power mode, wherein performing the read operation is based at least in part on loading the indication of the active region of the non-volatile memory device to the cache.

3. The memory system of claim 1 , wherein the controller is further configured to cause the memory system to:
transmit, to a host system, a portion of the mapping between the logical addresses and the physical addresses of the non-volatile memory device, wherein storing the indication of the active region of the non-volatile memory device is based at least in part on transmitting the portion of the mapping to the host system.

4. The memory system of claim 3 , wherein the active region of the non-volatile memory device correspond to the physical addresses of the non-volatile memory device included in the portion of the mapping transmitted to the host system.

5. The memory system of claim 1 , wherein the controller is further configured to cause the memory system to:
determine whether the physical address of the read command is associated with the active region based at least in part on the indication stored in the non-volatile memory device, wherein performing the read operation is based at least in part on determining that the physical address of the read command is associated with the active region.

6. The memory system of claim 5 , wherein the indication of the active region of the non-volatile memory device comprises a starting address and a quantity of addresses in the active region associated with one or more physical addresses of the non-volatile memory device, and the controller is further configured to cause the memory system to:
compare the physical address associated with the read command with the starting address and the quantity of addresses associated with the active region, wherein determining that the physical address of the read command of the non-volatile memory device is associated with the active region is based at least in part on the comparing.

7. The memory system of claim 5 , wherein the indication of the active region of the non-volatile memory device comprises a bitmap associated with one or more physical addresses of the non-volatile memory device, and the controller is further configured to cause the memory system to:
compare at least one bit associated with the read command to the bitmap stored to the cache, wherein determining that the physical address of the read command of the non-volatile memory device is associated with the active region is based at least in part on the comparing.

8. The memory system of claim 1 , wherein the first power mode comprises a lower power mode than the second power mode.

9. The memory system of claim 1 , wherein the second power mode is associated with executing received commands and the first power mode is associated with deactivating one or more components associated with the memory system.

10. A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:
receive, at a memory system, a command for entering a first power mode, wherein the memory system comprises a non-volatile memory device and a cache for storing a mapping between logical addresses and physical addresses of the non-volatile memory device;
store an indication of an active region of the non-volatile memory device that is configured for use as part of a host performance booster mode based at least in part on receiving the command;
enter the first power mode based at least in part on storing the indication;
receive a read command that includes a physical address of the non-volatile memory device in the active region of the non-volatile memory device based at least in part on entering the first power mode;
transition to a second power mode from the first power mode based at least in part on receiving the read command; and
perform, while the non-volatile memory device is operating in the second power mode, a read operation using the physical address of the non-volatile memory device based at least in part on receiving the read command.

11. The non-transitory computer-readable medium of claim 10 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
loading, to the cache, the indication of the active region of the non-volatile memory device based at least in part on transitioning to the second power mode, wherein performing the read operation is based at least in part on loading the indication of the active region of the non-volatile memory device to the cache.

12. The non-transitory computer-readable medium of claim 10 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
transmit, to a host system, a portion of the mapping between the logical addresses and the physical addresses of the non-volatile memory device, wherein storing the indication of the active region of the non-volatile memory device is based at least in part on transmitting the portion of the mapping to the host system.

13. The non-transitory computer-readable medium of claim 12 , wherein the active region of the non-volatile memory device correspond to the physical addresses of the non-volatile memory device included in the portion of the mapping transmitted to the host system.

14. The non-transitory computer-readable medium of claim 10 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:
determine whether the physical address of the read command is associated with the active region based at least in part on the indication stored in the non-volatile memory device, wherein performing the read operation is based at least in part on determining that the physical address of the read command is associated with the active region.

15. The non-transitory computer-readable medium of claim 14 , wherein the indication of the active region of the non-volatile memory device comprises a starting address and a quantity of addresses in the active region associated with one or more physical addresses of the

Assignees

• Micron Technology Inc

Inventors

• Zhao Bin
• Wang Lingyun

Classifications

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title