Clock generation circuit

US12050484B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12050484-B2
Application numberUS-201917051637-A
CountryUS
Kind codeB2
Filing dateApr 17, 2019
Priority dateMay 1, 2018
Publication dateJul 30, 2024
Grant dateJul 30, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A clock generation circuit includes a mode-locked laser that generates an optical pulse, a photodiode that photoelectrically converts the optical pulse generated by the mode-locked laser, and a filter that attenuates at least one of a DC component and a harmonic component of the mode-locked laser included in an electric signal output from the photodiode.

First claim

Opening claim text (preview).

The invention claimed is: 1. A clock generation circuit comprising: a mode-locked laser that generates an optical pulse; a photodetector that photoelectrically converts the optical pulse generated by the mode-locked laser into an electric clock signal, wherein the electric clock signal comprises a DC component and a harmonic component; an amplifier that amplifies the electric clock signal output from the photodetector to reduce jitter in the electric clock signal, wherein a first cutoff frequency on a lower band side of the amplifier is higher than a frequency of the DC component of the electric clock signal output from the photodetector, and wherein a second cutoff frequency on a higher band side of the amplifier is lower than a frequency of the harmonic component of the electric clock signal output from the photodetector; a first matching circuit between an output terminal of the photodetector and an input terminal of the amplifier, wherein the first matching circuit matches an impedance of the photodetector and the amplifier at a repetition frequency of the mode-locked laser; a second matching circuit between an output terminal of the amplifier and an input terminal of a subsequent circuit connected to the amplifier, wherein the second matching circuit matches an impedance of the amplifier and the subsequent circuit at the repetition frequency of the mode-locked laser, wherein each of the first matching circuit and second matching circuits includes: a first series resonator comprising a first series circuit composed of a first inductor and a first capacitor connected series in a signal line, wherein the first series resonator has a resonance frequency set to the repetition frequency of the mode-locked laser; a second series resonator comprising a second series circuit composed of a second inductor and a second capacitor between the signal line and a negative power supply line, wherein the second series resonator has a resonance frequency set to the frequency of the harmonic component of the mode-locked laser; a first parallel resonator comprising a first parallel circuit composed of a third inductor connected in series in the signal line and a third capacitor connected in parallel with the third inductor, wherein the first parallel resonator has a resonance frequency set to the frequency of the DC component or the frequency of the harmonic component of the mode-locked laser; or a second parallel resonator comprising a second parallel circuit composed of a fourth inductor between the signal line and the negative power supply line and a fourth capacitor connected in parallel with the fourth inductor, wherein the second parallel resonator has a resonance frequency set to the repetition frequency of the mode-locked laser. 2. The clock generation circuit according to claim 1 , wherein the amplifier includes a frequency peaking circuit having a center frequency set to the repetition frequency of the mode-locked laser. 3. A clock generation circuit comprising: a mode-locked laser that generates an optical pulse; a photodetector that photoelectrically converts the optical pulse generated by the mode-locked laser into an electric clock signal, wherein the electric clock signal comprises a DC component and a harmonic component; an amplifier that amplifies the electric clock signal output from the photodetector to reduce jitter in the electric clock signal, wherein a first cutoff frequency on a lower band side of the amplifier is higher than a frequency of the DC component of the electric clock signal output from the photodetector, and wherein a second cutoff frequency on a higher band side of the amplifier is lower than a frequency of the harmonic component of the electric clock signal output from the photodetector; a first matching circuit between an output terminal of the photodetector and an input terminal of the amplifier, wherein the first matching circuit matches an impedance of the photodetector and the amplifier at a repetition frequency of the mode-locked laser; a second matching circuit between an output terminal of the amplifier and an input terminal of a subsequent circuit connected to the amplifier, wherein the second matching circuit matches an impedance of the amplifier and the subsequent circuit at the repetition frequency of the mode-locked laser, wherein the amplifier comprises: a first parallel resonator comprising a first parallel circuit composed of a first inductor between a positive power supply line and an input signal line and a first capacitor connected in parallel with the first inductor, wherein the first parallel resonator has a resonance frequency set to the repetition frequency of the mode-locked laser; a second parallel resonator comprising a second parallel circuit composed of a second inductor between the positive power supply line and a positive power supply terminal of the amplifier and a second capacitor connected in parallel with the second inductor, wherein the second parallel resonator has a resonance frequency set to the frequency of the harmonic component of the mode-locked laser; or a third parallel resonator comprising a third parallel circuit composed of a third inductor between a negative power supply terminal of the amplifier and a negative power supply line and a third capacitor connected in parallel with the third inductor, wherein the third parallel resonator has a resonance frequency set to the frequency of the harmonic component of the mode-locked laser. 4. The clock generation circuit according to claim 3 , wherein each of the first matching circuit and second matching circuits includes: a first resonator comprising a first laminated inductor, wherein the first resonator has a resonance frequency set to the frequency of the DC component or the frequency of the harmonic component of the mode-locked laser; or a second resonator comprising a second laminated inductor, wherein the second resonator has a resonance frequency set to the repetition frequency of the mode-locked laser. 5. A clock generation circuit comprising: a mode-locked laser that generates an optical pulse; a photodetector that photoelectrically converts the optical pulse generated by the mode-locked laser into an electric clock signal, wherein the electric clock signal comprises a DC component and a harmonic component; an amplifier that amplifies the electric clock signal output from the photodetector to reduce jitter in the electric clock signal, wherein a first cutoff frequency on a lower band side of the amplifier is higher than a frequency of the DC component of the electric clock signal output from the photodetector, and wherein a second cutoff frequency on a higher band side of the amplifier is lower than a frequency of the harmonic component of the electric clock signal output from the photodetector; a first matching circuit between an output terminal of the photodetector and an input terminal of the amplifier, wherein the first matching circuit matches an impedance of the photodetector and the amplifier at a repetition frequency of the mode-locked laser; a second matching circuit between an output terminal of the amplifier and an input terminal of a subsequent circuit connected to the amplifier, wherein the second matching circuit matches an impedance of the amplifier and the subsequent circuit at the repetition frequency of the mode-locked laser, wherein the amplifier comprises: a first resonator comprising a first laminated inductor, wherein the first resonator has a resonance frequency set to the repetition frequency of the mode-locked laser; a second resonator comprising a second laminated inductor, wherein the second resonator has a resonance frequency set to the frequency of the harmonic component of the mode-locked laser; or a third resonator comprising a third laminated indu

Assignees

Inventors

Classifications

  • with FET's (H03F3/085 takes precedence) · CPC title

  • H03F1/223Primary

    with MOSFET's · CPC title

  • by the use, as active elements, of opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled · CPC title

  • controlled by light · CPC title

  • Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

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Frequently asked questions

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What does patent US12050484B2 cover?
A clock generation circuit includes a mode-locked laser that generates an optical pulse, a photodiode that photoelectrically converts the optical pulse generated by the mode-locked laser, and a filter that attenuates at least one of a DC component and a harmonic component of the mode-locked laser included in an electric signal output from the photodiode.
Who is the assignee on this patent?
Nippon Telegraph & Telephone
What technology area does this patent fall under?
Primary CPC classification H03F1/223. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 30 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).