Method for preparing semiconductor structure and semiconductor structure

Patent metadata

Field	Value
Publication number	US-12048138-B2
Application number	US-202117502324-A
Country	US
Kind code	B2
Filing date	Oct 15, 2021
Priority date	Mar 29, 2021
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

The present application provides a method for preparing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method for preparing a semiconductor structure includes: providing a base; forming a support layer having capacitor holes and electric contact structures; forming a first dielectric layer in the capacitor holes, the first dielectric layer surrounding first intermediate holes; forming a first electrode layer in the first intermediate holes, the first electrode layer filling the first intermediate holes; removing part of the support layer to form second intermediate holes; forming a second dielectric layer in the second intermediate holes, the first dielectric layer and the second dielectric layer forming a dielectric layer; and, forming a second electrode layer on the dielectric layer.

First claim

The invention claimed is:

1. A method for preparing a semiconductor structure, comprising:
providing a base, the base comprising a plurality of active areas;
forming a support layer on the base, and forming a plurality of electric contact structures in the support layer, the electric contact structures being in one-to-one correspondence to the active areas, wherein the support layer comprises a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer successively stacked, the first support layer is arranged on the base, and the electric contact structures are arranged in the first support layer;
forming a plurality of capacitor holes arranged at intervals in the support layer, each of the capacitor holes exposing each of the electric contact structures;
forming a first dielectric layer on sidewalls of the capacitor holes, the electric contact structures being exposed in first intermediate holes surrounded by the first dielectric layer, wherein a bottom surface of the first dielectric layer close to the base is located in the first support layer, and the bottom surface of the first dielectric layer close to the base is flush with top surfaces of the electric contact structures;
forming a first electrode layer in the first intermediate holes, the first electrode layer filling the first intermediate holes, the first dielectric layer and the first electrode layer forming intermediate capacitor structures;
removing part of the support layer to form second intermediate holes, the second intermediate holes exposing outer circumferential surfaces of the intermediate capacitor structures;
forming a second dielectric layer in the second intermediate holes, the first dielectric layer and the second dielectric layer forming a dielectric layer; and
forming a second electrode layer on the dielectric layer, the second electrode layer, the dielectric layer and the first electrode layer forming capacitor structures.

2. The method for preparing a semiconductor structure according to claim 1 , wherein the forming a first dielectric layer on sidewalls of the capacitor holes comprises:
forming an initial first dielectric layer on the sidewalls and bottom walls of the capacitor holes and a top surface of the support layer; and
removing part of the initial first dielectric layer on the bottom walls of the capacitor holes and the top surface of the support layer, and reserving part of the initial first dielectric layer on the sidewalls of the capacitor holes, the part of the initial first dielectric layer that is reserved forming the first dielectric layer.

3. The method for preparing a semiconductor structure according to claim 2 , wherein material of the first dielectric layer is a dielectric material with a high dielectric constant.

4. The method for preparing a semiconductor structure according to claim 3 , wherein the dielectric material comprises at least one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx or AlOx.

5. The method for preparing a semiconductor structure according to claim 1 , wherein the of removing part of the support layer comprises:
removing part of the support layer by dry etching, a reserved part of the support layer being used to support the intermediate capacitor structures, and the reserved part of the support layer forming the second intermediate holes exposing the outer circumferential surfaces of the intermediate capacitor structures.

6. The method for preparing a semiconductor structure according to claim 5 , wherein the removing part of the support layer by dry etching comprises:
patterning the third support layer, to form first etching holes in the third support layer, the first etching holes exposing the second sacrificial layer, the first etching holes being located between adjacent parts of first electrode layer; and
removing the second sacrificial layer, part of the second support layer and the first sacrificial layer, to form the second intermediate holes in the support layer, the second intermediate holes exposing the outer circumferential surfaces of the intermediate capacitor structures.

7. The method for preparing a semiconductor structure according to claim 6 , wherein the removing the second sacrificial layer, part of the second support layer and the first sacrificial layer, to form the second intermediate holes in the support layer comprises:
removing the second sacrificial layer;
etching the second support layer along the first etching holes, to form second etching holes in the second support layer, the second etching holes exposing the first sacrificial layer; and
removing the first sacrificial layer.

8. The method for preparing a semiconductor structure according to claim 1 , wherein the forming a second dielectric layer in the second intermediate holes comprises: forming, in the second intermediate holes and on the first dielectric layer, the second dielectric layer covering the first dielectric layer.

9. The method for preparing a semiconductor structure according to claim 8 , wherein the second dielectric layer is made of same material as the first dielectric layer.

10. The method for preparing a semiconductor structure according to claim 1 , wherein the forming a second electrode layer on the dielectric layer comprises: forming, in the second intermediate holes and on the second dielectric layer, the second electrode layer covering the second dielectric layer.

11. The method for preparing a semiconductor structure according to claim 10 , wherein materials of the first electrode layer and the second electrode layer comprise titanium nitride.

12. The method for preparing a semiconductor structure according to claim 1 , wherein the forming a support layer on the base and forming a plurality of electric contact structures in the support layer, the electric contact structures being in one-to-one correspondence to the active areas comprises:
forming a plurality of recesses in the first support layer, the recesses being in one-to-one correspondence to the active areas; and
forming the electric contact structures in the recesses, the top surfaces of the electric contact structures being lower than a top surface of the first support layer.

13. The method for preparing a semiconductor structure according to claim 12 , wherein material of the electric contact structures comprises tungsten.

14. The method for preparing a semiconductor structure according to claim 13 , wherein materials of the first support layer, the second support layer and the third support layer comprise silicon nitride, and materials of the first sacrificial layer and the second sacrificial layer comprise silicon oxide.

15. A semiconductor structure, the semiconductor structure is prepared by the method for preparing a semiconductor structure according to claim 1 ;
wherein the semiconductor structure comprises the base, the support layer arranged on the base and the capacitor structures, and the capacitor structures comprise the first electrode layer, and the dielectric layer and the second electrode layer successively arranged around the first electrode layer.

Assignees

• Changxin Memory Tech Inc

Inventors

• Zhan Kangshu
• Wan Qiang
• Xu Penghui
• Liu Tao
• Li Sen
• Xia Jun

Classifications

• H10D1/716

  having vertical extensions · CPC title

• H10D1/043 Primary

  using patterning processes to form electrode extensions, e.g. etching · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title