Semiconductor arrangement and method of manufacture

Patent metadata

Field	Value
Publication number	US-12048137-B2
Application number	US-202117404260-A
Country	US
Kind code	B2
Filing date	Aug 17, 2021
Priority date	Mar 19, 2021
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.

First claim

What is claimed is:

1. A semiconductor arrangement, comprising:
a memory array comprising bitcells; and
a peripheral logic block for accessing the bitcells, comprising:
a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block; and
a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.

2. The semiconductor arrangement of claim 1 , wherein the peripheral logic block comprises twelve nanostructures including the first nanostructure and the second nanostructure, associated with four bitcells of the memory array.

3. The semiconductor arrangement of claim 1 , comprising:
a third nanostructure adjacent the first nanostructure formed over a first semiconductor layer having a first conductivity type, wherein the first nanostructure is formed over a second semiconductor layer having a second conductivity type different than the first conductivity type.

4. The semiconductor arrangement of claim 3 , wherein:
the first nanostructure comprises a header transistor comprising a first gate and a first source/drain region coupled to a power supply terminal;
the third nanostructure comprises a logic device for reading values stored in the bitcells, the logic device comprising a second gate and a second source/drain region; and
the semiconductor arrangement comprises:
a source/drain contact connected to the first source/drain region and the second source/drain region to provide a power signal received by the header transistor at the power supply terminal to the logic device.

5. The semiconductor arrangement of claim 3 , wherein:
the first nanostructure comprises a header transistor comprising a first gate and a first source/drain region coupled to a power supply terminal;
the third nanostructure comprises a logic device for reading values stored in the bitcells, the logic device comprising a second gate and a second source/drain region; and
the semiconductor arrangement comprises:
a first source/drain contact connected to the first source/drain region;
a second source/drain contact connected to the second source/drain region; and
a conductive line connected to the first source/drain contact and the second source/drain contact to provide a power signal received by the header transistor at the power supply terminal to the logic device.

6. The semiconductor arrangement of claim 1 , wherein the first nanostructure and the second nanostructure are center aligned.

7. The semiconductor arrangement of claim 1 , wherein the first nanostructure and the second nanostructure are edge aligned.

8. The semiconductor arrangement of claim 1 , wherein:
the first logic unit comprises at least one of a write driver, write logic, a read column multiplexer, a sense amplifier, data output circuitry, or a pre-charge/equalization circuit; and
the second logic unit comprises at least one of a write assist circuit, a built-in self-test/data input circuit, or a column redundancy circuit.

9. The semiconductor arrangement of claim 1 , comprising:
a diffusion break structure between the first nanostructure and the second nanostructure.

10. The semiconductor arrangement of claim 9 , wherein the diffusion break structure comprises a dielectric material.

11. The semiconductor arrangement of claim 9 , comprising:
a first gate structure over the first nanostructure; and
a second gate structure over the second nanostructure, wherein the diffusion break structure is parallel to the first gate structure and the second gate structure.

12. A semiconductor arrangement, comprising:
a memory array comprising bitcells; and
a peripheral logic block for accessing the bitcells, comprising:
a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block;
a second nanostructure having a second width less than the first width for providing power to a second logic unit of the peripheral logic block;
a third nanostructure having the first width and adjacent the first nanostructure; and
a fourth nanostructure having the second width and adjacent the second nanostructure.

13. The semiconductor arrangement of claim 12 , wherein:
the first nanostructure and the second nanostructure have a first spacing; and
the second nanostructure and the fourth nanostructure have a second spacing different than the first spacing.

14. The semiconductor arrangement of claim 12 , wherein:
the first logic unit comprises at least one of column select logic, write driver logic, write column select logic, sense amplifier logic, or data driver logic; and
the second logic unit comprises at least one of column redundancy logic, built-in self-test logic, data input logic, or write assist logic.

15. A semiconductor arrangement, comprising:
a memory array comprising bitcells; and
a peripheral logic block for accessing the bitcells, comprising:
a well region having a longest dimension extending in a first direction;
a first active region row overlying the well region and having a longest dimension extending in the first direction; and
a diffusion break structure overlying the first active region row and extending in a second direction, wherein:
a first portion of the first active region row on a first side of the diffusion break structure has a first width measured in the second direction,
a second portion of the first active region row on a second side of the diffusion break structure opposite the first side has a second width measured in the second direction, and
the second width is smaller than the first width.

16. The semiconductor arrangement of claim 15 , comprising:
a gate structure overlying the first active region row on the first side of the diffusion break structure, wherein the gate structure has a longest dimension extending in the second direction.

17. The semiconductor arrangement of claim 16 , comprising:
a dummy gate structure overlying the first active region row on the second side of the diffusion break structure, wherein the dummy gate structure has a longest dimension extending in the second direction.

18. The semiconductor arrangement of claim 15 , comprising:
a dummy gate structure overlying the first active region row on the second side of the diffusion break structure.

19. The semiconductor arrangement of claim 15 , comprising:
a second active region row extending in the first direction, wherein:
the diffusion break structure overlies the second active region row,
a first portion of the second active region row on the first side of the diffusion break structure has a third width measured in the second direction,
a second portion of the second active region row on the second side of the diffusion break structure has a fourth width measured in the second direction, and
the fourth width is different than the third width.

20. The semiconductor arrangement of claim 19 , wherein:
the first portion of the first active region row is spaced apart from the first portion of the second active region row by a first spacing measured in the second direction,
the second portion of the first active region row is spaced apart from the second portion of the second active region row by a second spacing measured in the second direction, and
the first spacing is less than the second spacing.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Po-Sheng
• Wang Ru-Yu
• Lin Yangsyu
• Xiao You-Cheng

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10D84/856

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title