Finite impulse response input digital-to-analog converter

Patent metadata

Field	Value
Publication number	US-12047086-B2
Application number	US-202217980105-A
Country	US
Kind code	B2
Filing date	Nov 3, 2022
Priority date	Nov 3, 2021
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

First claim

What is claimed is:

1. A digital-to-analog converter comprising:
an integrator;
an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising:
a respective input resistance; and
a pair of differential tap elements; and

control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter;
wherein:
a first tap element of each member of the plurality of parallel taps is coupled between a first polarity of a digital input signal to the digital-to-analog converter and an inverting input of the integrator; and
a second member of each member of the plurality of parallel taps is coupled between a second polarity of a digital input signal to the digital-to-analog converter and a non-inverting input of the integrator.

2. A digital-to-analog converter comprising:
an integrator;
an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising:
a respective input resistance; and
a pair of differential tap elements, wherein each member of the plurality of parallel taps has a respective signal delay, such that at least two of the respective signal delays are different; and

control circuitry configured to selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

3. The digital-to-analog converter of claim 2 , wherein the respective signal delay for each member of the plurality of parallel taps is different.

4. The digital-to-analog converter of claim 2 , wherein the control circuitry is further configured to selectively enable and disable particular members of the plurality of parallel taps in order to control the analog gain of the digital-to-analog converter and to combine delay characteristics of enabled members of the plurality of parallel taps in order to generate desired filter characteristics for the input network.

5. The digital-to-analog converter of claim 2 , wherein the control circuitry is further configured to, when selectively enabling and disabling a particular member of the plurality of parallel taps, delay a control signal for enabling or disabling the particular member based on the respective signal delay for the particular member.

6. A digital-to-analog converter comprising:
an integrator;
an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising:
a respective input resistance; and
a pair of differential tap elements; and

control circuitry configured to:
selectively enable and selectively disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter; and
selectively enable and disable an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.

7. The digital-to-analog converter of claim 6 , wherein the first group and the second group are separated temporally from each other in order to facilitate matching of an input signal received by the digital-to-analog converter and an output of a component downstream of the digital-to-analog converter.

8. The digital-to-analog converter of claim 6 , wherein the control circuitry is further configured to, when enabling or disabling additional members of the plurality of parallel taps to modify the analog gain, alternate between tap delays that decrease a duration between a first center of the first group and a second center of the second group and tap delays that increase the duration.

9. The digital-to-analog converter of claim 8 , wherein the control circuitry is further configured to maintain the first center at approximately 25% of a pulse width of an input signal received by the digital-to-analog converter and at approximately 75% of a pulse width of the input signal.

10. A method comprising, in a digital-to-analog converter having an integrator and an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance, and including a pair of differential tap elements and wherein a first tap element of each member of the plurality of parallel taps is coupled between a first polarity of a digital input signal to the digital-to-analog converter and an inverting input of the integrator and a second member of each member of the plurality of parallel taps is coupled between a second polarity of a digital input signal to the digital-to-analog converter and a non-inverting input of the integrator;
selectively enabling and selectively disabling particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

11. A method comprising, in a digital-to-analog converter having an integrator and an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance and having a respective signal delay, such that at least two of the respective signal delays are different:
selectively enabling and selectively disabling particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter.

12. The method of claim 11 , wherein the respective signal delay for each member of the plurality of parallel taps is different.

13. The method of claim 11 , further comprising selectively enabling and disabling particular members of the plurality of parallel taps in order to control the analog gain of the digital-to-analog converter and to combine delay characteristics of enabled members of the plurality of parallel taps in order to generate desired filter characteristics for the input network.

14. The method of claim 11 , further comprising, when selectively enabling and disabling a particular member of the plurality of parallel taps, delaying a control signal for enabling or disabling the particular member based on the respective signal delay for the particular member.

15. A method comprising, in a digital-to-analog converter having an integrator and an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps comprising a respective input resistance:
selectively enabling and selectively disabling particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter; and
selectively enabling and disabling an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.

16. The method of claim 15 , wherein the first group and the second group are separated temporally from each other in order to facilitate matching of an input signal received by the digital-to-analog converter and an output of a component downstream of the digital-to-analog converter.

17. The method of claim 15 , further comprising, when selectively enabling and disabling additional members of the plurality of parallel taps to modify the analog

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Astrachan Paul M
• Zhang Lingli
• Melanson John L
• Kelton James

Classifications

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/74

  Simultaneous conversion · CPC title

• H03M1/80

  using weighted impedances (H03M1/76 takes precedence) · CPC title

• H03M1/0626

  by filtering · CPC title

• H03M1/0607

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title