Circuits and methods for set and reset signals

Patent metadata

Field	Value
Publication number	US-12047083-B2
Application number	US-202117519490-A
Country	US
Kind code	B2
Filing date	Nov 4, 2021
Priority date	Nov 4, 2021
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

In one particular implementation, a circuit includes: a flip flop; and an AND gate, where the circuit is configured to generate edge-triggered set and reset input signals. In another implementation, a method includes: providing, by a digital locked loop (DLL), a plurality of phase outputs; determining, by respective logic circuits, respective pulses to be selected for an output clock corresponding to each of the plurality phase outputs; shifting respective selection windows of the pulses such that each of the selection windows fully overlap the corresponding respective determined pulses; and selecting the pulses.

First claim

What is claimed is:

1. A circuit comprising:
a flip-flop; and
an AND gate, wherein:
the circuit is configured to generate edge-sensitive set and reset signals, the circuit comprises solely the flip-flop and the AND gate, and
the output of the flip-flop is provided as a feedback to the AND gate to generate the edge-sensitive reset signal transmitted to the flip-flop.

2. The circuit of claim 1 , wherein the flip-flop comprises a D-flip-flop.

3. The circuit of claim 2 , wherein:
an output of the D-flip-flop is a first input of the AND gate,
a reset input signal is a second input of the AND gate,
the output of the AND gate is the edge-sensitive reset signal.

4. The circuit of claim 1 , wherein a D input to the flip-flop is set to a digital “1”.

5. The circuit of claim 1 , wherein a set input signal of the circuit corresponds to a rising edge of an output clock signal of a phase selector circuit, and wherein a reset input signal of the circuit corresponds to a falling edge of the output clock signal of the phase selector circuit.

6. The circuit of claim 5 , wherein the set input signal and reset input signal correspond to rising edges of different delayed locked loop (DLL) output phases.

7. A circuit comprising:
a plurality of logic circuits configured to generate set and reset signals; and
an edge-triggered reset-set (RS) latch configured to receive the set and reset signals, and output edge-triggered set and reset signals, wherein the plurality of logic circuits comprise:
first and second state machine logic circuits;
first, second, third, and fourth data latches;
first, second, third, and fourth NAND gates;
first and second NOR gates; and
a pulser circuit.

8. The circuit of claim 7 , wherein the plurality of logic circuits comprise circuits comprise clock phase-shifting circuitry and clock phase selector circuitry.

9. The circuit of claim 8 , wherein the clock phase-shifting circuitry comprises: a phase locked loop (PLL) and a digital locked loop (DLL), and wherein the clock phase selector circuitry comprises: first and second state machine logic circuits, first and second data latches; first and second multiplexers, and a pulser circuit.

10. The circuit of claim 8 , wherein the clock phase selector circuitry is configured to shift a respective clock mask to fully select a clock signal pulse.

11. The circuit of claim 7 , wherein the edge-triggered RS latch comprises: a flip flop; and an AND gate.

12. A circuit comprising:
a D-flip-flop; and
an AND gate, wherein:
the circuit is configured to generate edge-sensitive set and reset signals, an output of the D-flip-flop is a first input of the AND gate, a reset input signal is a second input of the AND gate,
the output of the AND gate is the edge sensitive reset signal transmitted as an input of the D-flip-flop.

13. A circuit comprising:
a flip-flop; and
an AND gate, wherein:
the circuit is configured to generate edge-sensitive set and reset signals, a set input signal corresponds to a rising edge of an output clock signal of a phase selector circuit,
a reset input signal corresponds to a falling edge of the output clock signal of the phase selector circuit, and
the edge-sensitive reset signal is an input of the flip-flop.

14. A circuit comprising:
a plurality of logic circuits configured to generate set and reset signals; and
an edge-triggered reset-set (RS) latch configured to receive the set and reset signals, and output edge-triggered set and reset signals, wherein the plurality of logic circuits comprise clock phase-shifting circuitry and clock phase selector circuitry, wherein the clock phase selector circuitry is configured to shift a respective clock mask to fully select a clock signal pulse.

15. The circuit of claim 14 , wherein the clock phase-shifting circuitry comprises: a phase locked loop (PLL) and a digital locked loop (DLL), and wherein the clock phase selector circuitry comprises: first and second state machine logic circuits, first and second data latches; first and second multiplexers, and a pulser circuit.

16. The circuit of claim 14 , wherein the DLL is configured to provide a plurality of phase outputs.

17. The circuit of claim 16 , wherein each of the plurality of logic circuits are configured to determine a respective pulse to be selected for an output clock corresponding to each of the plurality of phase outputs.

18. The circuit of claim 17 , wherein a selection window is configured to be shifted to overlap the corresponding determined pulse.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Boujamaa El Mehdi
• Labbe Benoit
• Bull David Michael

Classifications

• H03L7/0814

  the phase shifting device being digitally controlled · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03L7/091 Primary

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title