Parallel-to-serial conversion circuit, parallel-to-serial conversion circuit layout, and memory

Patent metadata

Field	Value
Publication number	US-12047069-B2
Application number	US-202217849033-A
Country	US
Kind code	B2
Filing date	Jun 24, 2022
Priority date	Jan 10, 2022
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where the first input end is configured to receive high level signal, the second input end is configured to receive low level signal, the control ends are connected to selection unit and the output end is connected to a serial wire, and the selection unit is configured to receive selection signal and at least two branch signals, and is configured to select, based on the selection signal, one of the branch signals and transmit a selected branch signal to the parallel branch; the serial wire, configured to organize signals output by the parallel branches into a serial signal; and a drive unit, connected to the serial wire for enhancing drive capability of the serial wire, where an output end of the drive unit is configured to output the serial signal.

First claim

The invention claimed is:

1. A parallel-to-serial conversion circuit, comprising:
a plurality of parallel branches, each comprising a first input end, a second input end, control ends and an output end,
wherein the first input end is configured to receive a high level signal, the second input end is configured to receive a low level signal, the control ends are connected to a selection unit, and the output end is connected to a serial wire, and
wherein the selection unit is configured to receive a selection signal and at least two branch signals, and configured to select, based on the selection signal, one of the at least two branch signals and transmit a selected branch signal to a parallel branch of the plurality of parallel branches;
the serial wire, configured to organize signals output by the plurality of parallel branches into a serial signal; and
a drive unit, connected to the serial wire, for enhancing drive capability of the serial wire, wherein an output end of the drive unit is configured to output the serial signal;
wherein the selection unit comprises a multiplexer and a selection sub-unit,
wherein the multiplexer is configured to only receive two branch signals of the at least two branch signals, and the multiplexer is configured to be connected to the selection sub-unit;
wherein the selection sub-unit is configured to receive a selection command and generate the selection signal based on the selection command, and the selection command is an internal clock signal; and
wherein the multiplexer is configured to select, based on the selection signal, one of the two branch signals and transmit the selected branch signal to the parallel branch through one of the control ends.

2. The parallel-to-serial conversion circuit of claim 1 , wherein a period of the selection signal is n times of a period of the internal clock signal, and n is a branch number of the plurality of parallel branches.

3. The parallel-to-serial conversion circuit of claim 1 , wherein at most one of the selection signal or a branch signal of the at least two branch signals received by a same selection unit is a continuous signal.

4. The parallel-to-serial conversion circuit of claim 1 , wherein in the selection signals received by the selection units connected to the plurality of parallel branches, high levels are alternately distributed.

5. The parallel-to-serial conversion circuit of claim 1 , wherein in the selection signals received by the selection units connected to the plurality of parallel branches, high levels have an overlapped part.

6. The parallel-to-serial conversion circuit of claim 1 , wherein each parallel branch of the plurality of parallel branches comprises a switch Positive-channel Metal-Oxide-Semiconductor (PMOS) transistor and a switch Negative-channel Metal-Oxide-Semiconductor (NMOS) transistor,
wherein a gate of the switch PMOS transistor and a gate of the switch NMOS transistor are used as the control ends of the parallel branch for connecting the selection unit;
a source of the switch PMOS transistor and a drain of the switch NMOS transistor are connected to the serial wire;
a drain of the switch PMOS transistor is used as the first input end of the parallel branch for receiving the high level signal; and
a source of the switch NMOS transistor is used as the second input end of the parallel branch for receiving the low level signal.

7. The parallel-to-serial conversion circuit of claim 1 , wherein the drive unit comprises two inverters, wherein an input end of a first inverter of the two inverters is connected to the serial wire, and an output end of the first inverter is connected to an input end of a second inverter of the two inverters; and an output end of the second inverter is configured to output the serial signal.

8. The parallel-to-serial conversion circuit of claim 7 , wherein the first inverter or the second inverter comprises a drive Positive-channel Metal-Oxide-Semiconductor (PMOS) transistor and a drive Negative-channel Metal-Oxide-Semiconductor (NMOS) transistor,
wherein a gate of the drive PMOS transistor is connected to a gate of the drive NMOS transistor, and a source of the drive PMOS transistor is connected to a drain of the drive NMOS transistor; and
a drain of the drive PMOS transistor is configured to receive the high level signal, and a source of the drive NMOS transistor is configured to receive the low level signal.

9. A parallel-to-serial conversion circuit layout, configured to form the parallel-to-serial conversion circuit of claim 1 , the parallel-to-serial conversion circuit layout comprising
parallel branch layouts, each configured to form the parallel branch, and form the selection unit connected to the parallel branch; and
a drive unit layout, configured to form the drive unit,
wherein each of the parallel branch layouts and the drive unit layout are disposed in different layout layers; and layout layers where the parallel branch layouts are disposed are symmetrically arranged with respect to a layout layer where the drive unit layout is disposed; and
the serial wires connecting the parallel branch layouts and the drive unit layout are symmetrically arranged with respect to the layout layer where the drive unit layout is disposed.

10. The parallel-to-serial conversion circuit layout of claim 9 , wherein projections of the parallel branch layouts and the drive unit layout in a direction perpendicular to the layout layers are partially overlapped.

11. The parallel-to-serial conversion circuit layout of claim 9 , wherein projections of the parallel branch layouts and the drive unit layout in a direction perpendicular to the layout layers are not overlapped.

12. A memory having a parallel-to-serial conversion circuit, wherein the parallel-to-serial conversion circuit comprises:
a plurality of parallel branches, each comprising a first input end, a second input end, control ends and an output end,
wherein the first input end is configured to receive a high level signal, the second input end is configured to receive a low level signal, the control ends are connected to a selection unit, and the output end is connected to a serial wire, and
wherein the selection unit is configured to receive a selection signal and at least two branch signals, and configured to select, based on the selection signal, one of the at least two branch signals and transmit a selected branch signal to a parallel branch of the plurality of parallel branches;
the serial wire, configured to organize signals output by the plurality of parallel branches into a serial signal; and
a drive unit, connected to the serial wire, for enhancing drive capability of the serial wire, wherein an output end of the drive unit is configured to output the serial signal;
wherein the selection unit comprises a multiplexer and a selection sub-unit,
wherein the multiplexer is configured to only receive two branch signals of the at least two branch signals, and the multiplexer is configured to be connected to the selection sub-unit;
wherein the selection sub-unit is configured to receive a selection command and generate the selection signal based on the selection command, and the selection command is an internal clock signal; and
wherein the multiplexer is configured to select, based on the selection signal, one of the two branch signals and transmit the selected branch signal to the parallel branch through one of the control ends.

13. A memory using the parallel-to-serial conversion circuit layout of claim 9 in a layout framework of the memory.

Assignees

• Changxin Memory Tech Inc

Inventors

• Huang Keqin
• Ji Kangling

Classifications

• H03K19/1737 Primary

  using multiplexers (H03K19/1738 takes precedence) · CPC title

• H03K19/1774

  for global signals, e.g. clock, reset · CPC title

• G11C16/0425

  comprising cells containing a merged floating gate and select transistor · CPC title

• G11C7/1066

  Output synchronization · CPC title

• G11C2207/107

  Serial-parallel conversion of data or prefetch · CPC title