Electroforming process using an inversion-invariant linear ECC, and associated device

Patent metadata

Field	Value
Publication number	US-12046284-B2
Application number	US-202218076304-A
Country	US
Kind code	B2
Filing date	Dec 6, 2022
Priority date	Dec 23, 2021
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

An electroforming process for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder. An electroforming device performing electroforming through write operations to such a resistive memory and to a method for checking a write operation.

First claim

The invention claimed is:

1. A method for checking a write operation to a resistive memory of a memory device including a memory controller and an encoder computing an inversion-invariant linear error correction code, the method comprising the following steps:
requesting reading of a codeword written to an initial address, the codeword having been written by a write device connected directly to the encoder and having directly received, as write value instruction, values from the encoder, and checking whether all bits of this codeword all have one and a same logic value from among two possible logic values “0” or “1”; and
if all of the bits of this codeword all have the same logic value “0” or “1”, reading a status register of the memory controller in order to check a presence or absence of a correctable or non-correctable error in the codeword that has just been read; and depending on a result of the check:
signaling a write error;
or ending the method;
if all of the bits of this codeword do not all have the same logic value “0” or “1”, signaling a write error.

2. The method according to claim 1 , wherein the steps are implemented in order to check writing of a codeword in an electroforming operation.

3. The method according to claim 1 , wherein the steps are implemented in order to check writing of a codeword after steps of:
requesting a write operation to the memory device at an initial address corresponding to a selection of multiple resistors, with data to be written comprising k data bits all having one and a same first logic value from among two possible logic values “0” or “1”;
encoding the k data bits with the inversion-invariant linear error correction code so as to obtain a codeword comprising the data bits and r check bits, such that the check bits are dependent on an odd number of the data bits, resulting in the data bits and the check bits all having the same first logic value; and
writing the codeword to the selected resistors of said resistive memory, the memory controller writing the codeword to the selected resistors in 1T1R or 2T2R mode.

4. A device for checking a write operation to a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code and an associated decoder, the memory device being connected to an external processor, the checking device comprising means for implementing the steps of the method according to claim 1 .

5. The method according to claim 1 further comprising an electroforming process for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder, the process comprising the following steps:
requesting a write operation to the memory device at an initial address corresponding to a selection of multiple resistors, with data to be written comprising k data bits all having one and the same first logic value, called electroforming value, from among two possible logic values “0” and “1”;
encoding the k data bits with the inversion-invariant linear error correction code so as to obtain a codeword comprising the data bits and r check bits, such that the check bits are dependent on an odd number of the data bits, resulting in the data bits and the check bits all having the same first logic value; and
writing, by way of the write device connected directly to the encoder and directly receiving, as write value instruction, the values from the encoder, the codeword to the selected resistors of said resistive memory, the memory controller carrying out a write operation in 1T1R mode corresponding to an individual write operation for each resistor, each resistor being put into a high-impedance or low-impedance state according to the respective logic value of each bit of the codeword, the memory controller applying write conditions allowing the electroforming.

6. The method according to claim 5 , the process comprising the following subsequent steps:
requesting a read operation by the memory controller at the initial address in the resistive memory to which said codeword has been written and comparing the read value with an expected value and, if said values do not match, saving an electroforming address in a status register of the memory controller and/or in a register of an external processor connected to the memory device,
incrementing or decrementing the initial address, so as to obtain a new address corresponding to the selection of resistors other than those of the initial address; and
checking whether this new address is out of range:
if so, ending the process;
if not, reiterating the steps of claim 1 at the new address.

7. The method according to claim 5 , the electroforming process comprising the following subsequent steps:
supplying the read codeword to a decoder able to supply k data bits that are corrected if necessary based on the check bits, the decoder being able to inform a status register of the memory controller indicating the presence or absence of a correctable or non-correctable error in the codeword that has just been read;
and wherein the step of comparing the read value and an expected value includes an operation of consulting said status register of the controller.

8. The method according to claim 5 , the electroforming process comprising the following subsequent steps:
requesting, via an external processor, a read operation at the initial address and/or at a new address and checking whether all of the data bits returned to said processor, obtained at output from a decoder that received the read codeword, all have one and the same logic value from among two possible logic values “0” or “1”;
if all of the data bits all have the same expected logic value “0” or “1”, reading the status register of the memory controller in order to check the presence or absence of an error that has been corrected by said decoder in the codeword that has just been read; and, depending on the result of the check:
signaling an electroforming error; or
ending the process;
if all of the data bits do not all have the same logic value “0” or “1”, signaling an electroforming error.

9. The method according to claim 5 , the steps of the process being iterated at least once with data to be written wherein the logic value of the bits is different from the logic value of the bits of a previous iteration.

10. A electroforming device for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder, the electroforming device comprising means for implementing the steps of the method according to claim 5 .

11. The electroforming device according to claim 10 , wherein the means comprise a host processor, the steps of the electroforming process according to claim 5 being implemented by interactions between the host processor and the memory controller.

12. The method according to claim 5 , wherein the inversion-invariant linear error correction code is of a type SEC, SEC-DED, DEC, DEC-TED, TEC, and/or TEC-QED.

Assignees

• Commissariat Energie Atomique

Inventors

• Giraud Bastien
• Gherman Valentin
• Evain Samuel

Classifications

• G11C2013/0083

  Write to perform initialising, forming process, electro forming or conditioning · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title