Shift register, gate driving circuit and display panel

Patent metadata

Field	Value
Publication number	US-12046181-B2
Application number	US-202318299866-A
Country	US
Kind code	B2
Filing date	Apr 13, 2023
Priority date	Jan 29, 2021
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A shift register, a gate driving circuit, and a display panel. The shift register includes a first input module, a second input module, a first output module, a second output module, a first output control module, and a second output control module, where the first input module is configured to control the potential of a first node according to a first start signal and a first clock signal, the second input module is configured to control the potential of a second node according to a second start signal and the first clock signal, and the second start signal and the first start signal have opposite potentials; the first output module includes a first coupling unit configured to couple the potential of a third node according to the potential of a first output terminal in the case where the potential of the first output terminal jumps.

First claim

What is claimed is:

1. A shift register, comprising:
a first input module configured to control a potential of a first node according to a first start signal and a first clock signal;
a second input module configured to control a potential of a second node according to a second start signal and the first clock signal, wherein the second start signal and the first start signal have opposite potentials;
a first output module configured to transmit the first potential signal or a second potential signal to a first output terminal of the shift register according to the potential of the first node and a potential of a third node, and comprising a first coupling unit configured to couple the potential of the third node according to a potential of the first output terminal in a case where the potential of the first output terminal jumps;
a second output module configured to transmit the first potential signal or the second potential signal to a second output terminal of the shift register according to a potential of a fourth node and the potential of the first output terminal, and comprising a second coupling unit configured to couple the potential of the fourth node according to a potential of the second output terminal in a case where the potential of the second output terminal jumps;
a first output control module configured to control the potential of the third node according to the potential of the first node, the potential of the second node, a first potential signal, and a second clock signal; and
a second output control module configured to control the potential of the fourth node according to the potential of the first node, the potential of the second node, the first potential signal, and the second clock signal.

2. The shift register of claim 1 , wherein the second node is electrically connected to the third node; and the first output control module comprises:
a first sub-output control unit configured to, under the control of the first node and the second node, pull down the potential of the second node to a potential lower than a potential of the second potential signal and the potential of the third node to a potential lower than a potential of the second potential signal in a case where the second clock signal jumps from a first potential to a second potential; and
a second sub-output control unit configured to control the potential of the third node according to the first potential signal.

3. The shift register of claim 2 , wherein the first sub-output control unit further comprises:
a first transistor,
a second transistor, and
a first capacitor, wherein a gate of the first transistor is connected to the second node and a second terminal of the first capacitor, a first electrode of the first transistor is configured to be input into the second clock signal, and a second electrode of the first transistor is connected to a first terminal of the first capacitor and a second electrode of the second transistor; and a gate of the second transistor is connected to the first node, and a first electrode of the second transistor is configured to be input into the first potential signal; and the second sub-output control unit further comprises:
a third transistor, wherein a gate of the third transistor is connected to the first node, a first electrode of the third transistor is configured to be input into the first potential signal, and a second electrode of the third transistor is connected to the third node.

4. The shift register of claim 3 , wherein the first output control module further comprises:
a fourth transistor connected between the second node and the third node, wherein a gate of the fourth transistor is connected to the second node.

5. The shift register of claim 1 , wherein the first node is electrically connected to the fourth node and; the second output control module comprises:
a third sub-output control unit, wherein the third sub-output control unit is configured to, under the control of the first node and the second node, pull down the potential of the first node a potential lower than the potential of the second potential signal and the potential of the fourth node to a potential lower than the potential of the second potential signal in a case where the second clock signal jumps from the first potential to the second potential; and
a fourth sub-output control unit, wherein the fourth sub-output control unit is configured to control the potential of the fourth node according to the first potential signal.

6. The shift register of claim 5 , wherein the third sub-output control unit further comprises;
a fifth transistor;
a sixth transistor; and
a second capacitor, wherein a gate of the fifth transistor is connected to the first node and a second terminal of the second capacitor, a first electrode of the fifth transistor is configured to be input into the second clock signal, and a second electrode of the fifth transistor is connected to a first terminal of the second capacitor and a second electrode of the sixth transistor; and a gate of the sixth transistor is connected to the second node, and a first electrode of the sixth transistor is configured to be input into the first potential signal; and the fourth sub-output control unit further comprises:
a seventh transistor, wherein a gate of the seventh transistor is connected to the second node, a first electrode of the seventh transistor is configured to be input into the first potential signal, and a second electrode of the seventh transistor is connected to the fourth node.

7. The shift register of claim 6 , wherein the second output control module further comprises:
an eighth transistor connected between the first node and the fourth node, wherein a gate of the eighth transistor is connected to the first node.

8. The shift register of claim 1 , wherein the first coupling unit is configured to couple the potential of the third node to a potential lower than a potential of the second potential signal in a case where the potential of the first output terminal jumps from a first potential to a second potential; and the first output module further comprises:
a first output unit configured to be turned on or off according to the potential of the first node and to transmit the first potential signal to the first output terminal in a case where the first output unit itself is on; and
a second output unit configured to be turned on or off according to the potential of the third node and to transmit the second potential signal to the first output terminal of the shift register in a case where the second output unit itself is on.

9. The shift register of claim 8 , wherein the first output unit further comprises:
a ninth transistor, wherein a gate of the ninth transistor is connected to the first node, a first electrode of the ninth transistor is configured to be input into the first potential signal, and a second electrode of the ninth transistor is connected to the first output terminal.

10. The shift register of claim 8 , wherein the second output unit further comprises:
a tenth transistor, wherein a gate of the tenth transistor is connected to the third node, a first electrode of the tenth transistor is configured to be input into the second potential signal, and a second electrode of the tenth transistor is connected to the first output terminal.

11. The shift register of claim 8 , wherein the first coupling unit further comprises:
a third capacitor, wherein a first terminal of the third capacitor is connected to the first output terminal, and a second terminal of the third capacitor is connected to the third node.

12. The shift register of claim 1 , wherein the second coupling unit is

Assignees

• Yungu Guan Tech Co Ltd
• Yungu Guan Tech Ltd

Inventors

• Guo Enqing
• Li Junfeng
• Gai Cuili
• Wang Ling

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title