Architecture and method for binary and unary in-memory sorting

Patent metadata

Field	Value
Publication number	US-12045166-B2
Application number	US-202218080666-A
Country	US
Kind code	B2
Filing date	Dec 13, 2022
Priority date	Dec 16, 2021
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

Disclosed herein is an architecture for in-memory sorting of data and methods by utilizing memristors crossbar arrays to perform in-memory sorting for both unary bit-stream and binary format data sets and method for utilizing same. Evaluations of the disclosed architecture and method reflect a significant reduction in energy costs and processing time as compared to currently available solutions.

First claim

We claim:

1. An architecture for in-memory sorting of binary input data sets comprising:
a power supply;
a clock device;
a network comprising a plurality of sorting units, each comprising:
a comparator comprising a memristor crossbar array; and
two multiplexors;

wherein the memristor crossbar array comprises:
n rows, wherein n is equal to the data set's number of bits;
m number of columns, wherein m is equal to (8+2n−2); and
a plurality of memristors arranged in said rows and columns;

wherein the separate data sets are each stored in separate columns of the memristor crossbar array.

2. The architecture of claim 1 , wherein the total number of sorting units is equal to (N×log 2(N)×(log 2(N)+1)/4), wherein N is equal to the number of inputs to the sorting network.

3. The architecture of claim 1 , wherein the sorting units are split into stages.

4. A method for in-memory sorting of two input bitstream data sets comprising:
(a) providing a memory architecture comprising:
a power supply;
a clock device;
a network comprising a plurality of sorting unites each comprising a memristor crossbar array;

(b) storing each data set in two columns in the memristor crossbar array;
(c) splitting the network of sorting units into two or more stages, wherein each stage comprises at least two inputs;
(d) sorting the inputs of each partition of sorting units, wherein such sorting in each partition is conducted in parallel and comprises:
i. comparing the input data sets for each sorting unit;
ii. deriving a maximum value from the sorting units for each partition;
iii. copying the maximum value found by the sorting operation in one partition as an input to another partition;
iv. repeating the copying step for all partitions;
v. repeating the above sorting steps until the sorting process is complete, wherein the total number of processing cycles is equal to S×(1+PC b )+CP, and wherein PC b comprises the number of cycles necessary to execute the sorting step for one partition, CP comprises the number of copy operations for the sorting steps for one partition, and S is the total number of sorting steps.

5. The method of claim 4 , wherein the total number of stages is equal to log 2(N)×(log 2(N)+1)/2, wherein Nis equal to the number of inputs to the sorting network.

6. The method of claim 4 , wherein the number of partitions of sorting units is the equal to the number of sorting units that can run in parallel.

7. The method of claim 4 , wherein the sorting step further comprises:
(a) for each bit in an input binary bitstream data set, a value of said bit for a data set (Data Set A) is compared to a similarly positioned bit in the other data set (Data Set B) to generate an Output 0 for each bit;
(b) comparing a first bit in Data Set A to the corresponding Output 0 for said bit to generate a corresponding Output 1;
(c) comparing a second bit in Data Set A to the corresponding Output 0 for said bit to generate a corresponding Output 1A;
(d) comparing a second bit in Data Set B to the corresponding Output 0 for said bit to generate a corresponding Output 1B;
(e) repeating steps (c) and (d) for remaining subsequent bits to obtain a corresponding Output 1A and Output 1B for each comparison operation;
(f) inverting a value of the first bits' corresponding Output 1 to obtain an Output 2;
(g) for the second bit in the data sets through bit n−1:
i. compare the corresponding Output 1A to Output 1B to obtain a corresponding Output 2B; and
ii. invert a value of the corresponding Output 1A to obtain an Output 2A;

(h) for the n bit, comparing the corresponding Output 1A to Output 1B to obtain a corresponding Output 2B;
(i) inversing the values of all Output 2Bs to obtain a corresponding Output 3 for each;
(j) comparing Output 2 and all Output 3s to obtain a corresponding Output 4;
(k) comparing the Output 2A for the second bit to the Outputs 2B for the third bit through nth bit to obtain a corresponding Output 4;
(l) comparing each subsequent Output 2A to the Outputs 2B for the sequential bit to obtain each corresponding Output 4, to where the last comparison is between Output 2A for bit n−1 and Output 2B for bit n;
(m) comparing all Output 4s to obtain an Output 5;
(n) copying Output 5 on one or more memristors in the same column of the memristor crossbar array as the memristor storing Output 5;
(o) inverting Output 5 to obtain an Output 6; and
(p) storing said Output 6 in a different column of memristors in the memristor crossbar array.

8. The method of claim 7 , wherein the compare steps are performed using a NOR operation through application of a preconfigured voltage to applicable sections of the memristor crossbar array.

9. The method of claim 4 , wherein the memory architecture further comprises two multiplexors and wherein the sorting step further comprises:
(a) initializing the memristors that are not holding input data sets or an output of a comparison to be reused to a low resistive state;
(b) initializing the input bitstream data set;
(c) executing the first multiplexer to produce a maximum value of the input data sets; and
(d) executing the second multiplexer to produce a minimum value of the input data sets.

10. The method of claim 4 , wherein the sorting step further comprises:
(a) for each bit in an input unary bitstream data set, inverting a value of a bit for one data set (Data Set A) and a value of a bit for a second data set (Data Set B) in one clock cycle;
(b) comparing a resulting inverted values for the bits of the two data sets through a NOR operation in a second clock cycle to produce the minimum value;
(c) storing the comparison results in the memristor columns where the above comparison step was performed; and
(d) for each bit in an input unary bitstream data set, comparing each bit of Data Set A to the corresponding bit in Data Set B through a NOR operation and then inversing the resulting value to obtain the maximum value.

11. The method of claim 10 , wherein the compare steps are performed using a NOR operation through application of a preconfigured voltage to applicable sections of the memristor crossbar array.

12. The method of claim 10 , wherein the number of memristors is directly proportional to the length of the input bitstream data sets.

13. The method of claim 4 , wherein the input bitstream data sets are in unary form and where the sorting process requires only five cycles to complete for each sorting unit regardless of width of the input bitstream data sets.

Assignees

• Univ Of Louisiana Lafayette
• Univ Louisiana At Lafayette

Inventors

• Najafi Mohammadhassan
• Alam Mohsen Riahi
• Taherinejad Nima

Classifications

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F2212/1016

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• H03K19/185

  using dielectric elements with variable dielectric constant, e.g. ferro-electric capacitors · CPC title

• G11C2013/0073

  Write using bi-directional cell biasing · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title