System for providing power to low power systems

Patent metadata

Field	Value
Publication number	US-12045116-B2
Application number	US-202318093907-A
Country	US
Kind code	B2
Filing date	Jan 6, 2023
Priority date	Jun 8, 2022
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A system comprises a microcontroller system comprising a CPU, an I/O module, and a microcontroller system power input, a power supply comprising a first power supply output providing power at a first power level, and a second power supply output providing power at a second power level, and a switch comprising a signal input communicatively coupled to the I/O module and configured to receive a status signal from the I/O module, a first switch power input electrically coupled to the first power supply output, a second switch power input electrically coupled to the second power supply output, and a switch power output electrically coupled to the microcontroller system power input and configured to output power to the microcontroller system.

First claim

What is claimed is:

1. A system comprising:
a processing system, the processing system comprising:
an input/output (I/O) module; and
a processing system power input;

a power supply, the power supply comprising:
a first power supply output, wherein the first power supply output provides power at a first power level; and
a second power supply output, wherein the second power supply output provides power at a second power level, and wherein the first power level is different than the second power level; and

a switch, the switch comprising:
a signal input, wherein the signal input is communicatively coupled to the I/O module and configured to receive a status signal from the I/O module;
a first switch power input electrically coupled to the first power supply output;
a second switch power input electrically coupled to the second power supply output; and
a switch power output electrically coupled to the processing system power input and configured to output power to the processing system from either the first power supply output or the second power supply output.

2. The system of claim 1 , wherein the switch alternates the output power to the processing system based on the status signal.

3. The system of claim 1 , wherein:
the processing system further comprises a second processing system power input, wherein the second processing system power input is electrically coupled to a second power domain of the processing system and wherein the processing system power input is electrically coupled to a first power domain of the processing system; and
a second switch, wherein the second switch is electrically coupled to the first power supply output, the second power supply output, and the I/O module.

4. The system of claim 3 , wherein the I/O module is configured to sequentially transmit a first status signal to the first switch and a second status signal to the second switch to sequentially alter the output power to first power domain and the second power domain.

5. The system of claim 1 , wherein the processing system further comprises:
a comparator configured to compare the output of the switch power output to a reference voltage.

6. The system of claim 1 , wherein the processing system includes a first power domain and a second power domain, wherein the processing system power input is electrically coupled to the first power domain, the processing system further comprising:
a second processing system power input, wherein the second processing system input is electrically coupled to the second power domain and one of the first power output and the second power output.

7. The system of claim 6 , further comprising:
a level shifter electrically coupled to the first power domain and the second power domain.

8. The system of claim 1 , wherein the status signal is based on a state of the processing system.

9. The system of claim 8 , wherein the state of the processing system is one or more of a sleep state, a functional sleep state, and an active state.

10. The system of claim 1 , wherein the processing system is a system on a chip and the switch is located external to the system on a chip.

11. The system of claim 1 , wherein only portions of the processing system alternate between the first power level and the second power level.

12. An external power source for a processing system, the external power source comprising:
a power supply, the power supply comprising;
a first power supply output configured to provide power at a first power level;
a second power supply output configured to provide power at a second power level, wherein the second power level is different than the first power level; and

a switch, the switch comprising:
a signal input configured to be communicatively coupled to the processing system;
a first switch power input electrically coupled to the first power supply output;
a second switch power input electrically coupled to the second power supply output; and
a switch power output configured to be electrically coupled to a processing system power input of the processing system and configured to output power to the processing system from either the first power supply output or the second power supply output.

13. The external power source of claim 12 , wherein the signal input is configured to receive a status signal from the processing system, and wherein the switch alternates the power output to the processing system between the first power level and the second power level based on the status signal.

14. The external power source of claim 12 , further comprising:
a secondary switch, the secondary switch comprising:
a second signal input configured to be communicatively coupled to the processing system;
a secondary first switch power input electrically coupled to the first power supply output;
a secondary second switch power input electrically coupled to the second power supply output; and
a secondary second switch power output configured to be electrically coupled to a second processing system power input of the processing system, wherein the second processing system power input is associated with a different power domain of the processing system than the processing system power input, and wherein the secondary second switch power output is configured to output power to the processing system.

15. A method for selectively outputting power to a processing system, the method comprising:
transmitting, by an input/output (I/O) module of the processing system to a signal input of a switch, a first status signal, wherein the first status signal is indicative of a first state of the processing system;
receiving, by the signal input of the switch, the first status signal;
outputting, by the switch in response to receipt of the first status signal, power to the processing system via a processing system power input of the processing system at a first power level;
transmitting, by the I/O module of the processing system to the signal input of the switch, a second status signal, wherein the second signal is indicative of a second state of the processing system;
receiving, by the signal input of the switch, the second status signal;
outputting, by the switch in response to receipt of the second status signal, power to the processing system via the processing system power input of the processing system at a second power level, wherein the second power level is different than the first power level.

16. The method of claim 15 , wherein the processing system power input of the processing system is associated with a first power domain, the method further comprising:
transmitting, by the I/O module of the processing system to a signal input of a second switch, the first status signal;
receiving, by the signal input of the second switch, the first status signal;
outputting, by the second switch in response to receipt of the first status signal, power to the processing system via a second processing system power input of the processing system at the first power level, wherein the second processing system power input of the processing system is associated with a second power domain of the processing system;
transmitting, by the I/O module of the processing system to the signal input of the second switch, the second status signal;
receiving, by the signal input of the second switch, the second status signal;
outputting, by the second switch in response to receipt of the second power signal, power to the processing system via the second processing system power input of the processing system at the first power level;
transmitting, by the I/O module of t

Assignees

• Ambiq Micro Inc

Inventors

• Bogue Ivan
• Mortazavi Yousof
• Coulon Jesse
• Srivastava Rajeev

Classifications

• G06F1/263

  Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title