Chip-on-film structure, display apparatus and method for manufacturing same

US12041829B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12041829-B2
Application numberUS-202117437012-A
CountryUS
Kind codeB2
Filing dateFeb 8, 2021
Priority dateApr 2, 2020
Publication dateJul 16, 2024
Grant dateJul 16, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides a chip-on-film structure, a display apparatus and a methods for manufacturing the display apparatus. The display apparatus includes: a base substrate; a bonding structure disposed on the base substrate; and a chip-on-film COF structure, wherein the COF structure and a side of the bonding structure that is away from the base substrate are clamped with each other, and the COF structure is bonded to the side of the bonding structure that is away from the base substrate; wherein when the COF structure and the bonding structure are bonded, the COF structure contacts both a first surface and a second surface of the bonding structure at the side of the bonding structure that is away from the base substrate, wherein the first surface is parallel to the base substrate, and the second surface is at an angle with the first surface.

First claim

Opening claim text (preview).

What is claimed is: 1. A display apparatus, comprising: a base substrate; a bonding structure, disposed on the base substrate; and a chip-on-film (COF) structure, wherein the COF structure and a side of the bonding structure that is away from the base substrate are clamped with each other, and the COF structure is bonded to the side of the bonding structure that is away from the base substrate; wherein when the COF structure and the bonding structure are bonded, the COF structure contacts both a first surface and a second surface of the bonding structure at the side of the bonding structure that is away from the base substrate, wherein the first surface is parallel to the base substrate, and the second surface is at an angle with the first surface. 2. The display apparatus according to claim 1 , wherein the bonding structure comprises a plurality of bonding pattern layers that are sequentially laminated on the base substrate and first insulating layers respectively disposed between each two adjacent bonding pattern layers; the COF structure comprises a plurality of COF layers that are sequentially laminated and second insulating layers respectively disposed between each two adjacent COF layers; the plurality of bonding pattern layers is in one-to-one correspondence with the plurality of COF layers, and a side of each bonding pattern layer that is away from the base substrate is bonded with a corresponding COF layer; and edges at the side of the plurality of bonding pattern layers that is away from the base substrate are arranged like a stair-step; the first surface comprises at least a part of an area of a surface of the bonding pattern layer that is away from the base substrate; and the second surface comprises at least one side surface of at least one bonding pattern layer. 3. The display apparatus according to claim 2 , wherein for an i th bonding pattern layer and an (i+1) th bonding pattern layer sequentially arranged along a direction away from the base substrate among the plurality of bonding pattern layers, the i th bonding pattern layer protrudes beyond the (i+1) th bonding pattern layer, where i≥1. 4. The display apparatus according to claim 3 , wherein a first orthographic projection is within a second orthographic projection, and an area of the first orthographic projection is smaller than an area of the second orthographic projection; the first orthographic projection is an orthographic projection of the (i+1) th bonding pattern layer on the base substrate, and the second orthographic projection is an orthographic projection of the i th bonding pattern layer on the base substrate. 5. The display apparatus according to claim 3 , wherein the plurality of bonding pattern layers comprises a first bonding pattern layer and at least one second bonding pattern layer; the at least one second bonding pattern layer is disposed between the base substrate and the first bonding pattern layer; and the second bonding pattern layer comprises a first sub-pattern and a second sub-pattern spaced from each other, wherein both the first sub-pattern and the second sub-pattern are bonded with a COF layer corresponding to the second bonding pattern layer; a side of a first sub-pattern of the i th bonding pattern layer away from a second sub-pattern of the i th bonding pattern layer protrudes beyond the (i+1) th bonding pattern layer, and a side of the second sub-pattern of the i th bonding pattern layer away from the first second sub-pattern of the i th bonding pattern layer protrudes beyond the (i+1) th bonding pattern layer. 6. The display apparatus according to claim 3 , wherein for a first insulating layer between the i th bonding pattern layer and the (i+1) th bonding pattern layer, at at least one side of the i th bonding pattern layer, the i th bonding pattern layer protrudes beyond the first insulating layer, and the first insulating layer protrudes beyond the (i+1) th bonding pattern layer. 7. The display apparatus according to claim 6 , wherein for the first insulating layer between the i th bonding pattern layer and the (i+1) th bonding pattern layer, at each of the at least one side, the first insulating layer protrudes beyond the (i+1) th bonding pattern layer for a length of smaller than or equal to 60 microns. 8. The display apparatus according to claim 7 , wherein the length is larger than or equal to 20 microns and is smaller than or equal to 40 microns. 9. The display apparatus according to claim 2 , wherein the bonding pattern layer comprises at least one first pin; the COF layer comprises at least one second pin; the first pin of the bonding pattern layer is in one-to-one correspondence with the second pin of the COF layer; and a side of each first pin away from the base substrate is bonded with a corresponding second pin; and the display apparatus further comprises a plurality of leads disposed on the base substrate, the at least one first pin of the bonding pattern layer is in one-to-one correspondence with the plurality of leads, and each first pin is connected to a corresponding lead. 10. The display apparatus according to claim 9 , further comprising a connecting structure disposed on the base substrate, wherein at least part of the at least one first pin is connected to a lead corresponding to the first pin through the connecting structure. 11. The display apparatus according to claim 1 , further comprising a flexible printed circuit (FPC) bonded with the COF structure, wherein a side of the COF structure away from the FPC is bonded with the bonding structure. 12. A method for manufacturing a display apparatus, comprising: providing a base substrate and a chip-on-film (COF) structure; forming a bonding structure on the base substrate; and bonding the COF structure with a side of the bonding structure that is away from the base substrate, wherein the COF structure and the side of the bonding structure that is away from the base substrate are clamped with each other; wherein when the COF structure and the bonding structure are bonded, the COF structure contacts both a first surface and a second surface of the bonding structure at the side of the bonding structure that is away from the base substrate, wherein the first surface is parallel to the base substrate, and the second surface is at an angle with the first surface. 13. The method according to claim 12 , wherein forming the bonding structure on the base substrate comprises: forming a plurality of bonding pattern layers that are sequentially laminated on the base substrate and first insulating layers respectively disposed between each two adjacent bonding pattern layers, wherein edges at the side of the plurality of bonding pattern layers that is away from the base substrate are arranged like a stair-step; the first surface comprises at least a part of an area of a surface of the bonding pattern layer that is away from the base substrate; and the second surface comprises at least one side surface of at least one bonding pattern layer; the COF structure comprises a plurality of COF layers that are sequentially laminated and second insulating layers respectively disposed between each two adjacent COF layers; the plurality of bonding pattern layers is in one-to-one correspondence with the plurality of COF layers; and bonding the COF structure with the side of the bonding structure that is away from the base substrate comprises: bonding a side of each bonding pattern layer that is away from the base substrate with a corresponding COF layer. 14. The method according to claim 13 , wherein the bonding pattern layer comprises at least one first

Assignees

Inventors

Classifications

  • Display · CPC title

  • H05K1/189Primary

    characterised by the use of flexible or folded printed circuits · CPC title

  • Manufacture or treatment · CPC title

  • Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation · CPC title

  • Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads · CPC title

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What does patent US12041829B2 cover?
The present disclosure provides a chip-on-film structure, a display apparatus and a methods for manufacturing the display apparatus. The display apparatus includes: a base substrate; a bonding structure disposed on the base substrate; and a chip-on-film COF structure, wherein the COF structure and a side of the bonding structure that is away from the base substrate are clamped with each other, …
Who is the assignee on this patent?
Chengdu Boe Optoelect Tech Co, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H05K1/189. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 16 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).