Method for manufacturing buried word line transistor, transistor and memory

Patent metadata

Field	Value
Publication number	US-12041764-B2
Application number	US-202117449502-A
Country	US
Kind code	B2
Filing date	Sep 30, 2021
Priority date	Sep 16, 2020
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

A method for manufacturing a buried word line transistor can include the following operations. A semiconductor substrate having an active region is provided. A first trench is formed in the active region. A first insulation layer is formed on a side wall of the first trench. A bottom portion of the first trench is etched to form a second trench. A gate oxide layer is formed on a side wall of the first insulation layer and a bottom portion and a side wall of the second trench. A barrier layer is formed at a bottom portion and portion of a side wall of the gate oxide layer. A metal filler layer is formed on an inner side of the barrier layer. The first insulation layer is removed to form a side trench. A second insulation layer is formed at a top end of the side trench. A sealed air spacer layer is formed.

First claim

What is claimed is:

1. A method for manufacturing a buried word line transistor, comprising:
providing a semiconductor substrate having an active region, forming a first trench in the active region;
forming a first insulation layer on a side wall of the first trench, and etching a bottom portion of the first trench to form a second trench;
forming a gate oxide layer on a side wall of the first insulation layer and a bottom portion and a side wall of the second trench, forming a barrier layer at a bottom portion and portion of a side wall of the gate oxide layer, and forming a metal filler layer on an inner side of the barrier layer;
removing the first insulation layer to form a side trench between the gate oxide layer and the side wall of the first trench; and
forming a second insulation layer at a top end of the side trench and over the barrier layer and the metal filler layer, and therefore forming a sealed air spacer layer between the gate oxide layer and the side wall of the first trench, an upper surface of the second insulation layer and an upper surface of the substrate being located on the same horizontal plane.

2. The method of claim 1 , wherein the forming a first insulation layer on a side wall of the first trench, and etching a bottom portion of the first trench to form a second trench comprises:
forming a first insulation material layer at a bottom portion and a side wall of the first trench and on an upper surface of the substrate by using an atomic layer deposition process;
etching the first insulation material layer on the upper surface of the substrate and the first insulation material layer at the bottom portion of the first trench to form the first insulation layer; and
etching the substrate exposed at the bottom portion of the first trench to form a second trench, wherein a width of the second trench is smaller than a width of the first trench.

3. The method of claim 1 , wherein the forming a gate oxide layer on a side wall of the first insulation layer and a bottom portion and a side wall of the second trench, forming a barrier layer at a bottom portion and portion of a side wall of the gate oxide layer, and forming a metal filler layer on an inner side of the barrier layer comprises:
forming an oxide material layer on a surface of the first insulation layer, the bottom portion and the side wall of the second trench and an upper surface of the substrate by using a thin film deposition process;
forming a barrier material layer on a surface of the oxide material layer by using an atomic layer deposition process;
forming a metal material layer on a surface of the barrier material layer by using a chemical vapor deposition process, wherein the metal material layer fills the first trench and the second trench and covers the barrier material layer on the upper surface of the substrate; and
etching the metal material layer, the barrier material layer, and the oxide material layer on the upper surface of the substrate, and etching portion of the metal material layer and portion of the barrier material layer in the first trench to form the gate oxide layer, the barrier layer, and the metal filler layer.

4. The method of claim 1 , wherein the forming a second insulation layer at the top end of the side trench and over the barrier layer and the metal filler layer comprises:
forming a second insulation material layer at a top of the side trench, an inner side of the gate oxide layer, and an upper surface of the substrate by using a chemical vapor deposition process; and
etching the second insulation material layer to form the second insulation layer.

5. The method of claim 1 , wherein a bottom of the air spacer layer is lower than the upper surface of the metal filler layer.

6. The method of claim 5 , wherein a distance between the bottom of the air spacer layer and the upper surface of the metal filler layer is 5 to 20 nm.

7. The method of claim 1 , wherein an upper surface of the barrier layer is higher than an upper surface of the metal filler layer.

8. The method of claim 7 , wherein a distance between the upper surface of the barrier layer and the upper surface of the metal filler layer is 3 to 20 nm.

9. The method of claim 1 , wherein a depth of the first trench is 45 to 100 nm.

10. The method of claim 1 , wherein the second trench has a depth of 50 to 130 nm, and a width of 15 to 50 nm.

11. A buried word line transistor, comprising:
a semiconductor substrate comprising an active region;
a word line trench located in the active region;
a gate oxide layer located at a bottom portion and a side wall of the word line trench, an air spacer layer being formed on an outer side wall of the gate oxide layer;
a barrier layer covering a bottom portion and portion of a side wall of the gate oxide layer;
a metal filler layer filling a bottom portion of the word line trench and partially covering a surface of the barrier layer; and
a second insulation layer configured to seal the air spacer layer and fill a space over the barrier layer and the metal filler layer, an upper surface of the second insulation layer and an upper surface of the substrate being located on the same horizontal plane.

12. The buried word line transistor of claim 11 , wherein a bottom of the air spacer layer is lower than the upper surface of the metal filler layer.

13. The buried word line transistor of claim 11 , wherein a distance between the bottom of the air spacer layer and the upper surface of the metal filler layer is 5 to 20 nm.

14. The buried word line transistor of claim 11 , wherein an upper surface of the barrier layer is higher than the upper surface of the metal filler layer.

15. The buried word line transistor of claim 14 , wherein a distance between the upper surface of the barrier layer and the upper surface of the metal filler layer is 3 to 20 nm.

16. The buried word line transistor of claim 11 , wherein a depth of the air spacer layer is 45 to 100 nm.

17. The buried word line transistor of claim 11 , wherein the word line trench has a depth of 120 to 200 nm, and a width of 15 to 50 nm.

18. A memory, comprising a buried word line transistor comprising:
a semiconductor substrate comprising an active region;
a word line trench located in the active region;
a gate oxide layer located at a bottom portion and a side wall of the word line trench, an air spacer layer being formed on an outer side wall of the gate oxide layer;
a barrier layer covering a bottom portion and portion of a side wall of the gate oxide layer;
a metal filler layer filling a bottom portion of the word line trench and partially covering a surface of the barrier layer;
a second insulation layer configured to seal the air spacer layer and fill a space over the barrier layer and the metal filler layer, an upper surface of the second insulation layer and an upper surface of the substrate being located on the same horizontal plane; and
the memory further comprising a shallow trench isolation structure formed in the semiconductor substrate.

19. The memory of claim 18 , wherein a bottom of the air spacer layer is lower than the upper surface of the metal filler layer.

20. The memory of claim 18 , wherein a distance between the bottom of the air spacer layer and the upper surface of the metal filler layer is 5 to 20 nm.

Assignees

• Changxin Memory Tech Inc

Inventors

• Wu Gongyi
• Deng Nan
• Wang Yuchen

Classifications

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/488

  Word lines · CPC title

• H10B12/053 Primary

  the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383) · CPC title