Packaging substrate with low thermal resistance and low parasitic inductance

Patent metadata

Field	Value
Publication number	US-12040592-B2
Application number	US-202117445786-A
Country	US
Kind code	B2
Filing date	Aug 24, 2021
Priority date	May 28, 2021
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

A substrate may include a thermally conductive metal core having a top side and a bottom side, a first dielectric coating on the top side of the metal core, a second dielectric coating on the bottom side of the metal core, a first metal circuit layer formed above the first dielectric coating, and a second metal circuit layer formed under the second dielectric coating. In some implementations, the first dielectric coating and the second dielectric coating have thicknesses below sixty micrometers and respective thermal resistances under fifteen degrees Celsius per watt. In some implementations, one or more electrical currents flowing vertically across a dielectric coating have a low parasitic inductance based on the thickness of the dielectric coating, and the metal core may dissipate heat flowing across the dielectric coating and into the metal core.

First claim

What is claimed is:

1. A substrate, comprising:
a thermally conductive metal core having a top side and a bottom side;
a first dielectric coating on the top side of the metal core;
a second dielectric coating on the bottom side of the metal core,
wherein the first dielectric coating and the second dielectric coating have respective thicknesses that are less than sixty micrometers, and
wherein the first dielectric coating and the second dielectric coating have respective thermal resistances that are less than fifteen degrees Celsius per watt;

a first metal circuit layer formed above the first dielectric coating;
a second metal circuit layer formed under the second dielectric coating; and
a via through the first dielectric coating or the second dielectric coating,
wherein the via is filled with metal to provide an electrical connection to the metal core from the first metal circuit layer or the second metal circuit layer,
wherein one or more electrical currents flowing vertically across one or more of the first dielectric coating or the second dielectric coating, or horizontally along one or more of the metal core, the first metal circuit layer, or the second metal circuit layer, have a low parasitic inductance based on the respective thicknesses of the first dielectric coating and the second dielectric coating, and
wherein the metal core dissipates heat that flows across one or more of the first dielectric coating or the second dielectric coating and into the metal core.

2. The substrate of claim 1 , further comprising:
another via through the first dielectric coating, the metal core, and the second dielectric coating,
wherein the other via is filled with metal and a dielectric material to provide an electrical connection from the first metal circuit layer to the second metal circuit layer that is isolated from the metal core.

3. The substrate of claim 1 , wherein the first dielectric coating and the second dielectric coating include one or more of aluminum oxynitride (AlON), aluminum nitride (AlN), aluminum oxide (Al2O3), or aluminum phosphate (AlPO4).

4. The substrate of claim 1 , wherein the first dielectric coating and the second dielectric coating have respective thicknesses that are less than twenty-five micrometers.

5. The substrate of claim 1 , wherein the one or more electrical currents include an electrical current that flows between the metal core and the first metal circuit layer or the second metal circuit layer, and wherein the low parasitic inductance of the electrical current is based on the thickness of the one or more of the first dielectric coating or the second dielectric coating separating the metal core from the first metal circuit layer or the second metal circuit layer.

6. The substrate of claim 1 , further comprising:
a third dielectric coating on a top side of the first metal circuit layer;
a third metal circuit layer formed above the third dielectric coating; and
one or more additional vias through one or more of the first dielectric coating, the third dielectric coating, or the metal core to provide an electrical connection to the third metal circuit layer.

7. The substrate of claim 1 , further comprising:
a third dielectric coating on a bottom side of the second metal circuit layer;
a third metal circuit layer formed below the third dielectric coating; and
one or more additional vias through one or more of the first dielectric coating, the third dielectric coating, or the metal core to provide an electrical connection to the third metal circuit layer.

8. A substrate, comprising:
a metal core having a top side and a bottom side;
a first set of metal circuit layers formed above the top side of the metal core;
a second set of metal circuit layers formed below the bottom side of the metal core,
wherein each metal circuit layer in the first set of metal circuit layers and the second set of metal circuit layers is separated from at least one of the metal core or an adjacent metal layer by a dielectric layer having a thickness that is less than twenty-five micrometers and a thermal resistance under fifteen degrees Celsius per watt, and
wherein electrical current and heat flow vertically through the substrate; and

a via through the dielectric layer separating the metal core from a metal circuit layer,
wherein the via is filled with metal to provide an electrical connection to the metal core from at least one of the first set of metal circuit layers or the second set of metal circuit layers.

9. The substrate of claim 8 , wherein the dielectric layer includes aluminum oxynitride (AlON), aluminum nitride (AlN), aluminum oxide (Al2O3), or aluminum phosphate (AlPO4).

10. The substrate of claim 8 , further comprising:
another via through the metal core,
wherein the other via is filled with metal and a dielectric material to provide an electrical connection from a first metal circuit layer above the metal core to a second metal circuit layer below the metal core.

11. The substrate of claim 8 , wherein a parasitic inductance of the dielectric layer is based on the thickness of the dielectric layer, and wherein the thermal resistance of the dielectric layer is based on one or more of the thickness of the dielectric layer or a thermal conductivity of a dielectric material used in the dielectric layer.

12. A package, comprising:
a substrate that includes a cavity; and
a submount, bonded to the substrate in the cavity, wherein the submount includes:
a metal base block;
a dielectric coating on a top side of the metal base block,
wherein the dielectric coating has a thickness that is less than sixty micrometers; and

a metal circuit layer formed above the dielectric coating,
wherein electrical current and heat flow vertically through the submount; and

two or more vias through the dielectric coating,
wherein the two or more vias are filled with metal to provide an electrical connection from the metal circuit layer to the metal base block.

13. The package of claim 12 , wherein the dielectric coating includes aluminum oxynitride (AlON), aluminum nitride (AlN), aluminum oxide (Al2O3), or aluminum phosphate (AlPO4).

14. The package of claim 12 , wherein the submount is electrically bonded to the substrate by one or more conductive elements.

15. The package of claim 12 , wherein the submount is mechanically bonded to the substrate by an electrically insulative epoxy.

16. The package of claim 12 , wherein the metal base block is connected to ground and arranged to dissipate the heat that flows through the package.

17. The package of claim 12 , wherein the dielectric coating has a thermal resistance under fifteen degrees Celsius per watt.

18. The package of claim 12 , wherein the dielectric coating completely covers the top side of the metal base block except at a location of the two or more visa.

19. The substrate of claim 1 , wherein at least one of:
the first dielectric coating completely covers the top side of the metal core except at a location of the via, or
the second dielectric coating completely covers the bottom side of the metal core except at a location of the via.

20. The substrate of claim 8 , wherein the dielectric layer completely covers at least one of the top side of the metal core or the bottom side of the metal core except at a location of the via.

Assignees

• Lumentum Operations Llc

Inventors

• Shi Wei
• Huang Hao
• Cheung Siu Kwan
• Zhu Huanlin
• Zhu Lijun

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W40/10

  Arrangements for heating · CPC title