Fabricating sub-micron contacts to buried well devices

Patent metadata

Field	Value
Publication number	US-12040366-B2
Application number	US-202117303809-A
Country	US
Kind code	B2
Filing date	Jun 8, 2021
Priority date	Jul 27, 2020
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

A method for forming a semiconductor structure. Two isolation structures are formed in a semiconductor. A cavity is etched in the semiconductor between the two isolation structures in the semiconductor. Dopants are implanted into a bottom side of the cavity to form a doped region in the semiconductor below the cavity between the two isolation structures. A contact is formed in the cavity. The contact is on the doped region and in direct contact with the doped region.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a first silicon germanium layer;
a second silicon germanium layer;
a silicon layer between the first and second silicon germanium layers;
first and second shallow trench isolation structures extending through the first silicon germanium layer, the silicon layer and the second silicon germanium layer;
a first cavity on one side of the first shallow trench isolation structure, a second cavity between the first and second shallow trench isolation structures, and a third cavity on one side of the second shallow trench isolation structure;
first, second, and third active areas below the respective first, second and third cavities, wherein the first, second and third active areas are in contact with the silicon layer; and
first, second and third metal contacts in the respective first, second and third cavities, wherein the first, second and third metal contacts are formed by depositing metal in the first, second and third cavities, respectively, and wherein the first, second and third metal contacts are isolated from the silicon layer by the respective first, second and third active areas.

2. The semiconductor structure of claim 1 , wherein the first metal contact is in direct contact with the first active area, the second metal contact is in direct contact with the second active area, and the third metal contact is in direct contact with the third active area.

3. The semiconductor structure of claim 1 , wherein the first, second and third metal contacts are not in direct contact with the silicon layer, and wherein the first, second and third metal contacts are separated from the silicon layer by the respective first, second and third active areas.

4. The semiconductor structure of claim 1 , wherein the first and second shallow trench isolation structures are separated from the first, second and third active areas.

5. A semiconductor structure comprising:
a first silicon germanium layer;
a second silicon germanium layer;
a silicon layer between the first and second silicon germanium layers;
first, second and third cavities in the first silicon germanium layer;
a first shallow trench isolation structure between the first and second cavities and extending through the first silicon germanium layer, the silicon layer and the second silicon germanium layer;
a second shallow trench isolation structure between the third and second cavities and extending through the first silicon germanium layer, the silicon layer and the second silicon germanium layer;
first, second, and third active areas below the respective first, second and third cavities, wherein the first, second and third active areas are in contact with the silicon layer; and
first, second and third metal contacts in the respective first, second and third cavities, wherein the first, second and third metal contacts are formed by depositing metal in the first, second and third cavities, respectively, and wherein the first, second and third metal contacts are isolated from the silicon layer by the respective first, second and third active areas.

6. The semiconductor structure of claim 5 , wherein the first metal contact is in direct contact with the first active area, the second metal contact is in direct contact with the second active area, and the third metal contact is in direct contact with the third active area.

7. The semiconductor structure of claim 5 , wherein the first, second and third metal contacts are not in direct contact with the silicon layer, and wherein the first, second and third metal contacts are separated from the silicon layer by the respective first, second and third active areas.

8. The semiconductor structure of claim 5 , wherein the first and second shallow trench isolation structures are separated from the first, second and third active areas.

Assignees

• Boeing Co

Inventors

• Lee Kangmu Min
• Choi Maxwell Daehan
• Wright Jeffrey Alden
• Ha Wonill
• Jackson Clayton
• Jura Michael Pemberton
• Schmitz Adele
• Chappell James

Classifications

• H10P30/212

  Through-implantation · CPC title

• H10P30/206

  into Group III-V semiconductors · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title