Processing interrupt requests for autonomous systems and applications

Patent metadata

Field	Value
Publication number	US-12039362-B2
Application number	US-202217746366-A
Country	US
Kind code	B2
Filing date	May 17, 2022
Priority date	May 17, 2022
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

In various examples, a timer component that generates an event when an interrupt request has not yet been cleared within at least a predetermined amount of time.

First claim

What is claimed is:

1. A system comprising:
an interrupt controller component to receive an interrupt request;
at least one processor to implement an interrupt handler operating at a first risk classification level, the interrupt handler to clear the interrupt request from the interrupt controller component and
a timer component to generate an event when the interrupt request has not yet been cleared within at least a predetermined amount of time, the interrupt handler, the interrupt controller component, and the timer component collectively to operate at a second risk classification level that indicates a lower level of risk than the first risk classification level.

2. The system of claim 1 , wherein the interrupt controller component is implemented as a hardware circuit, and timer component is implemented using a virtual machine manager, the virtual machine manager being implemented using the at least one processor.

3. The system of claim 1 , wherein the at least one processor is further to implement a virtual machine manager that implements at least one of the timer component or the interrupt controller component.

4. The system of claim 1 , further comprising:
a hardware circuit having first and second portions, the interrupt controller component being implemented as the first portion and the timer component being implemented as the second portion.

5. The system of claim 1 , further comprising:
an event handler operating at the second risk classification level, the timer component to communicate the event to the event handler, the event handler to perform at least one corrective action or cause the at least one corrective action to be performed after the event handler receives the event.

6. The system of claim 5 , wherein the at least one processor is further to implement a virtual machine manager that implements the event handler.

7. The system of claim 5 , further comprising:
a non-maskable interrupt line, the event to be communicated to the operating system over the non-maskable interrupt line, and the operating system to implement the event handler.

8. The system of claim 1 , wherein the timer component is a first timer component,
the interrupt request is a first interrupt request associated with a first priority,
the predetermined amount of time is a first predetermined amount of time,
the interrupt controller component is to receive a second interrupt request associated with a second priority before the interrupt controller component receives the first interrupt request,
the first priority is greater than the second priority, and
the system further comprises a second timer component to determine when the second interrupt request has not yet been cleared within at least a second predetermined amount of time, the first timer component to cause the second timer component to pause when the first timer component receives the first interrupt request, the first timer component to cause the second timer component to resume when the first interrupt request has been cleared from the interrupt controller component.

9. The system of claim 1 , further comprising:
a System on a Chip (“Sort”) comprising the interrupt controller component and the timer component.

10. The system of claim 9 , wherein the system is at least one of an autonomous machine or a semi-autonomous machine, and the at least one of the autonomous machine or the semi-autonomous machine further comprises:
an event source to send the interrupt request to the interrupt controller component, the event source comprising or being connected to at least one sensor, the event source to generate the interrupt request when the at least one sensor indicates criteria has been satisfied.

11. A method comprising:
notifying an interrupt handler of an interrupt request wherein the interrupt handler is operating at a first risk classification level, the interrupt handler to clear the interrupt request;
starting a timer component based at least in part on the interrupt request; and
generating an event when the timer component indicates at least a predetermined amount of time has elapsed and the interrupt handler has not cleared the interrupt request, the interrupt handler and the timer component collectively operating at a second risk classification level that indicates a lower level of risk than the first risk classification level.

12. The method of claim 11 , further comprising:
receiving a second interrupt request, the interrupt request being a first interrupt request, the first and second interrupt requests having first and second priorities, respectively, wherein the first priority is greater than the second priority, the timer component being a first timer component; and
pausing a second timer component associated with the second interrupt request.

13. The method of claim 11 , wherein the interrupt request is received by an interrupt controller component that notifies the interrupt handler of the interrupt request; and
the interrupt handler attempts to handle the interrupt request before the event is generated.

14. The method of claim 11 , further comprising:
sending the event to an event handler that operates at the second risk classification level.

15. The method of claim 13 , wherein the timer component is implemented using a virtual machine manager, and
the interrupt controller component is implemented using a hardware circuit.

16. The method of claim 13 , wherein the timer component and the interrupt controller component are both implemented using at least one of a virtual machine manager or a hardware circuit.

17. The method of claim 11 , further comprising:
sending the event to an event handler that is implemented using a virtual machine manager.

18. The method of claim 11 , wherein the interrupt handler is implemented using an operating system, and the method further comprises:
sending the event to the operating system over a non-maskable interrupt line; and
performing, using the operating system, at least one corrective action in response to the event.

19. The method of claim 11 , further comprising:
sending the event to an event handler; and
performing, using the event handler, at least one corrective action in response to the event.

20. The method of claim 11 , wherein the timer component and the interrupt handler are components of an autonomous machine or a semi-autonomous machine, and the method further comprises:
sending the event to an event handler; and
returning, at least in part using the event handler, the autonomous machine or the semi-autonomous machine to a safe state in response to the event.

21. The method of claim 11 , further comprising:
generating, using an event source, the interrupt request when at least one sensor of the event source or connected to the event source indicates criteria has been satisfied; and
sending, using the event source, the interrupt request to an interrupt controller component that receives the interrupt request and notifies the interrupt handler of the interrupt request, the interrupt handler to attempt to handle the interrupt request before the event is generated.

22. The method of claim 11 , further comprising:
stopping the timer component when the interrupt handler clears the interrupt request before the predetermined amount of time has elapsed.

23. The method of claim 11 , further comprising:
receiving the predetermined amount of time from a configuration component;
storing the predetermined amo

Assignees

• Nvidia Corp

Inventors

• Stoppa Igor

Classifications

• G06F9/542

  Event management; Broadcasting; Multicasting; Notifications · CPC title

• G06F2209/481

  Exception handling · CPC title

• G06F9/4825 Primary

  Interrupt from clock, e.g. time of day · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title