Information processing device and compiler method

Patent metadata

Field	Value
Publication number	US-12039308-B2
Application number	US-202318160418-A
Country	US
Kind code	B2
Filing date	Jan 27, 2023
Priority date	May 10, 2022
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

A non-transitory computer-readable recording medium stores a program for causing a computer to execute a process, the process includes determining, for an n-dimensional array (n≥3) included in an instruction code in an innermost loop of a multiple loop included in a source code, whether array sizes of a first argument and a second argument match numbers of rotations of a first index and a second index in the multiple loop, respectively, when the array sizes match the numbers of rotations and when each initial value and each increment value of the first and second indexes is 1, replacing the first argument and the second argument of the n-dimensional array included in the instruction code with a third argument and changing the n-dimensional array to an (n−1)-dimensional array, and integrating a loop that uses the first index and a loop that uses the second index.

First claim

What is claimed is:

1. A non-transitory computer-readable recording medium storing a program for causing a computer to execute a process, the process comprising:
determining, for an n-dimensional array (n≥3) included in an instruction code in an innermost loop of a multiple loop included in a source code, whether array sizes of a first argument and a second argument match numbers of rotations of a first index that corresponds to the first argument and a second index that corresponds to the second argument in the multiple loop, respectively, the multiple loop being a loop with a hierarchical structure in which loops are nested;
when the array sizes match the numbers of rotations, respectively, and when an initial value of each of the first index and the second index is 1 and an increment value of each of the first index and the second index is 1, replacing the first argument and the second argument of the n-dimensional array included in the instruction code with a third argument and changing the n-dimensional array to an (n−1)-dimensional array; and
integrating a first loop that uses the first index and a second loop that uses the second index.

2. The non-transitory computer-readable recording medium according to claim 1 , the process further comprising:
changing the n-dimensional array to the (n−1)-dimensional array when a variable that indicates the first argument matches a control variable of the first index and a variable that indicates the second argument matches a control variable of the second index.

3. The non-transitory computer-readable recording medium according to claim 2 , the process further comprising:
changing the n-dimensional array to the (n−1)-dimensional array when the first argument and the second argument are adjacent to each other.

4. The non-transitory computer-readable recording medium according to claim 1 , the process further comprising:
integrating the first loop and the second loop by deleting the first loop and by changing a final value of the second index that corresponds to a third argument.

5. The non-transitory computer-readable recording medium according to claim 1 , the process further comprising:
obtaining candidates for loops to be integrated by using profile information that includes a code length of a code in each loop, a number of loop rotations of each loop, and a number of times the n-dimensional array is accessed in each loop in one rotation, the profile information being obtained when the source code is executed; and
determining the first loop and the second loop from the obtained candidates.

6. The non-transitory computer-readable recording medium according to claim 1 , the process further comprising:
determining the first loop and the second loop based on designation made by a user.

7. An information processing device, comprising:
a memory; and
a processor coupled to the memory and the processor configured to:
determine, for an n-dimensional array (n≥3) included in an instruction code in an innermost loop of a multiple loop included in a source code, whether array sizes of a first argument and a second argument match numbers of rotations of a first index that corresponds to the first argument and a second index that corresponds to the second argument in the multiple loop, respectively, the multiple loop being a loop with a hierarchical structure in which loops are nested;
when the array sizes match the numbers of rotations, respectively, and when an initial value of each of the first index and the second index is 1 and an increment value of each of the first index and the second index is 1, replace the first argument and the second argument of the n-dimensional array included in the instruction code with a third argument and changing the n-dimensional array to an (n−1)-dimensional array; and
integrate a first loop that uses the first index and a second loop that uses the second index.

8. A compiler method, comprising:
determining by a computer, for an n-dimensional array (n≥3) included in an instruction code in an innermost loop of a multiple loop included in a source code, whether array sizes of a first argument and a second argument match numbers of rotations of a first index that corresponds to the first argument and a second index that corresponds to the second argument in the multiple loop, respectively, the multiple loop being a loop with a hierarchical structure in which loops are nested;
when the array sizes match the numbers of rotations, respectively, and when an initial value of each of the first index and the second index is 1 and an increment value of each of the first index and the second index is 1, replacing the first argument and the second argument of the n-dimensional array included in the instruction code with a third argument and changing the n-dimensional array to an (n−1)-dimensional array; and
integrating a first loop that uses the first index and a second loop that uses the second index.

Assignees

• Fujitsu Ltd

Inventors

• Kimura Shigeru

Classifications

• G06F8/443

  Optimisation · CPC title

• G06F9/325

  for loops, e.g. loop detection or loop counter · CPC title

• G06F8/452 Primary

  Loops · CPC title

• G06F8/4452 Primary

  Software pipelining · CPC title