Current signature jammer of an integrated circuit

Patent metadata

Field	Value
Publication number	US-12039092-B2
Application number	US-202117544038-A
Country	US
Kind code	B2
Filing date	Dec 7, 2021
Priority date	Dec 8, 2020
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

The present description concerns an integrated circuit including, between first and second terminals having a first voltage applied therebetween, a load configured to execute instructions, a circuit for delivering a digital signal having at least two bits from a binary signal and a current output digital-to-analog converter controlled by the digital signal and coupled between the first and second terminals in parallel with the load.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first terminal and a second terminal, wherein a first voltage is applied between the first terminal and the second terminal;
a processor coupled between the first terminal and the second terminal, the processor configured to execute instructions and generate a first control signal of a binary kind;
a jamming circuit configured to:
receive the first control signal, and
generate a second control signal based on the first control signal, the second control signal being a digital signal having N bits, where N is an integer equal to or greater than two; and

a digital-to-analog converter configured to:
receive the second control signal, and
generate a jamming current based on the second control signal, the jamming current being a value between zero and a constant maximum current value and having 2 N number of possible values, and a current flowing from the first terminal to the second terminal being equal to a sum of a current draw from the processor and the jamming current.

2. The integrated circuit of claim 1 , wherein the digital-to-analog converter is further coupled between the first terminal and the second terminal, and the digital-to-analog converter is arranged in parallel with the processor.

3. The integrated circuit of claim 1 , wherein the processor comprises a power supply, the integrated circuit further comprising:
a regulator coupled between the first terminal and the second terminal, the regulator configured to deliver a second voltage to the power supply based on the first voltage, and
wherein the digital-to-analog converter is further coupled between the first terminal and the second terminal, and the digital-to-analog converter is coupled in parallel with the processor and the regulator.

4. The integrated circuit of claim 1 , wherein N equals three.

5. The integrated circuit of claim 1 , wherein the first control signal is a random signal.

6. The integrated circuit of claim 1 , wherein the jamming circuit comprises:
a plurality of flip-flops arranged in series, an operation of each flip-flop controlled by a clock signal, wherein a first flip-flop in the series is configured to receive the first control signal, and a last flip-flop in the series is configured to output the second control signal.

7. The integrated circuit of claim 6 , wherein a quantity of the plurality of flip-flops is greater than N.

8. The integrated circuit of claim 1 , further comprising a smoothing circuit configured to smooth the current consumed by the processor.

9. A method, comprising:
having a processor for executing instructions, the processor coupled between a first terminal and a second terminal;
applying a first voltage between the first terminal and the second terminal;
generating, by the processor, a first control signal of a binary kind;
generating, by a jamming circuit, a second control signal based on the first control signal, the second control signal being a digital signal having N bits, where N is an integer equal to or greater than two; and
generating, by a digital-to-analog converter, a jamming current based on the second control signal, the jamming current being a value between zero and a constant maximum current value and having 2 N number of possible values, and a current flowing from the first terminal to the second terminal being equal to a sum of a current draw from the processor and the jamming current.

10. The method of claim 9 , wherein the digital-to-analog converter is coupled between the first terminal and the second terminal, and the digital-to-analog converter is arranged in parallel with the processor.

11. The method of claim 9 , further comprising:
having a regulator coupled between the first terminal and the second terminal; and
generating, by the regulator, a second voltage to a power supply of the processor, the second voltage based on the first voltage.

12. The method of claim 9 , wherein N equals three.

13. The method of claim 9 , wherein the first control signal is a random signal.

14. The method of claim 9 , wherein the jamming circuit comprises:
a plurality of flip-flops arranged in series, an operation of each flip-flop controlled by a clock signal, wherein a first flip-flop in the series is configured to receive the first control signal, and a last flip-flop in the series is configured to output the second control signal.

15. A system comprising an integrated circuit, the integrated circuit comprising:
a first terminal and a second terminal, wherein a first voltage is applied between the first terminal and the second terminal;
a processor coupled between the first terminal and the second terminal, the processor configured to execute instructions and generate a first control signal of a binary kind;
a jamming circuit configured to:
receive the first control signal, and
generate a second control signal based on the first control signal, the second control signal being a digital signal having N bits, where N is an integer equal to or greater than two; and

a digital-to-analog converter configured to:
receive the second control signal, and
generate a jamming current based on the second control signal, the jamming current being a value between zero and a constant maximum current value and having 2 N number of possible values, and a current flowing from the first terminal to the second terminal being equal to a sum of a current draw from the processor and the jamming current.

16. The system of claim 15 , wherein the digital-to-analog converter is further coupled between the first terminal and the second terminal, and the digital-to-analog converter is arranged in parallel with the processor.

17. The system of claim 15 , wherein the processor comprises a power supply, the integrated circuit further comprising:
a regulator coupled between the first terminal and the second terminal, the regulator configured to deliver a second voltage to the power supply based on the first voltage, and
wherein the digital-to-analog converter is further coupled between the first terminal and the second terminal, and the digital-to-analog converter is coupled in parallel with the processor and the regulator.

18. The system of claim 15 , wherein N equals three.

19. The system of claim 15 , wherein the first control signal is a random signal.

20. The system of claim 15 , wherein the jamming circuit comprises:
a plurality of flip-flops arranged in series, an operation of each flip-flop controlled by a clock signal, wherein a first flip-flop in the series is configured to receive the first control signal, and a last flip-flop in the series is configured to output the second control signal.

Assignees

• Stmicroelectronics France
• St Microelectronics Alps Sas

Inventors

• Goulier Julien
• Bernon Pascal

Classifications

• H03K3/84

  Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H04L2209/08

  Randomization, e.g. dummy operations or using noise · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• G06F21/755 Primary

  with measures against power attack · CPC title