Processor package with universal optical input/output

Patent metadata

Field	Value
Publication number	US-12038858-B2
Application number	US-202017067334-A
Country	US
Kind code	B2
Filing date	Oct 9, 2020
Priority date	Oct 9, 2020
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

A processor package module comprises a substrate, one or more compute die mounted to the substrate, and one or more photonic die mounted to the substrate. The photonic die have N optical I/O links to transmit and receive optical I/O signals using a plurality of virtual optical channels, the N optical I/O links corresponding to different types of I/O interfaces excluding power and ground I/O. The substrate is mounted into a socket that support the power and ground I/O and electrical connections between the one or more compute die and the one or more photonic die.

First claim

What is claimed is:

1. A processor package module, comprising:
a substrate;
one or more compute die mounted to a first side of the substrate;
one or more photonic die mounted to the first side of the substrate, the one or more photonic die having N optical I/O links to transmit and receive optical I/O signals using a plurality of virtual optical channels, the N optical I/O links corresponding to different types of I/O interfaces, excluding power and ground I/O, wherein the plurality of virtual optical channels carry memory signals, storage signals, accelerator signals, system management signals, boot signals, and display signals; and
a socket onto which a second side of the substrate is mounted, the socket supporting the power and ground I/O and electrical connections between the one or more compute die and the one or more photonic die.

2. The processor package module of claim 1 , wherein second side of the socket includes electrical power and ground contacts.

3. The processor package module of claim 2 , wherein the socket does not include any electrical contacts dedicated to the plurality of I/O links corresponding to different types of I/O interfaces.

4. The processor package module of claim 2 , wherein the socket includes electrical contacts dedicated to the plurality of I/O links corresponding to different types of I/O interfaces, but the electrical contacts are inactive.

5. The processor package module of claim 2 , wherein the electrical power and ground contacts are located in an area of the socket located directly beneath the one or more compute die.

6. The processor package module of claim 2 , wherein the electrical power and ground contacts are in an area of the socket located below the one or more compute die and the one or more photonic die.

7. The processor package module of claim 1 , wherein the one or more photonic die each include optical ports.

8. The processor package module of claim 7 , wherein the optical ports are on a bottom of the one or more photonic die.

9. The processor package module of claim 7 , wherein the optical ports are on a top or an edge of the one or more photonic die.

10. The processor package module of claim 1 , wherein the socket comprises a land grid array (LGA) socket.

11. A processor chip complex, comprising:
a processor board; and
a plurality of processor package modules mounted to the processor board, ones of the processor package modules comprising:
a substrate;
one or more compute die mounted to a first side of the substrate;
one or more photonic die mounted to the first side of the substrate, the one or more photonic die having N optical I/O links to transmit and receive optical I/O signals using a plurality of virtual optical channels, the N optical I/O links corresponding to different types of I/O interfaces, excluding power and ground I/O, wherein the plurality of virtual optical channels of the N optical I/O links corresponding to different types of I/O interfaces transmit optical I/O signals for the compute die for any combination of memory signals, storage signals, accelerator signals, system management signals, boot signals, and display signals; and
a socket onto which a second side of the substrate is mounted, the socket mounting a corresponding one of the processor package modules to a front side of the processor board, the socket supporting only the power and ground I/O and electrical connections between the one or more compute die and the one or more photonic die.

12. The processor chip complex of claim 11 , wherein the socket comprises a land grid array (LGA) socket.

13. The processor chip complex of claim 11 , wherein the one or more photonic die includes a first set of optical ports and the processor board includes embedded optical links and a second set of optical ports located on an edge of the processor board to pass the optical I/O signals from the socket to the edge of the processor board.

14. The processor chip complex of claim 11 , wherein the optical I/O links are relayed from the processor board across multiple sets of optical ports to remote optically connected I/O devices.

15. The processor chip complex of claim 14 , wherein the remote optically connected I/O devices include any combination of a memory device, a storage device, an accelerator device, a system management controller, and a system boot device.

16. The processor chip complex of claim 14 , wherein the optical I/O links relayed to the remote optically connected I/O devices are dedicated to one of the socket, a server or a rack.

17. The processor chip complex of claim 14 , wherein the optical I/O links relayed to the remote optically connected I/O devices are shared between multiple servers.

18. The processor chip complex of claim 11 , further comprising an optical switch between the processor package modules and sets of optical ports located on an edge of the processor board.

19. A method of fabricating a processor chip complex, the method comprising:
fabricating a plurality of processor package modules using standard assembly processes, where ones of the processor package modules comprise one or more compute die and one or more photonic die both mounted to a first side of a substrate;
mounting the plurality of the processor package modules into respective LGA sockets;
testing the plurality of the processor package modules to provide pretested processor package modules;
mounting the pretested processor package modules to a processor board using the LGA sockets, and supplying power to each of the pretested processor package modules through the LGA sockets; and
optically connecting N optical I/O links corresponding to different types of I/O interfaces from a first set of optical ports on the photonic die of each of the processor package modules to a corresponding second set of optical ports on an edge of the processor board, wherein the N optical I/O links corresponding to the different types of I/O interfaces transmit optical I/O signals for the photonic die of each of the processor package modules for any combination of memory signals, storage signals, accelerator signals, system management signals, boot signals, and display signals.

20. The method of claim 19 , further comprising testing the processor chip complex.

21. The method of claim 19 , further comprising before or after testing, making optical fiber connections between the second set of optical ports on the edge of the processor board to remote I/O devices external to the processor chip complex.

22. The method of claim 19 , further comprising sharing the N optical I/O links relayed to remote I/O devices between multiple servers.

Assignees

• Intel Corp

Inventors

• Thakur Anshuman
• Subareddy Dheeraj
• Hossain Md Altaf
• Nalamalpu Ankireddy
• Kumashikar Mahesh
• Sane Sandeep

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• G06F2213/40

  Bus coupling · CPC title

• G06F13/4063

  Device-to-bus coupling · CPC title

• G06F13/20 Primary

  for access to input/output bus · CPC title