Display panel, method for manufacturing display panel, and display device

Patent metadata

Field	Value
Publication number	US-12035581-B2
Application number	US-201917255884-A
Country	US
Kind code	B2
Filing date	Nov 21, 2019
Priority date	Nov 21, 2019
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

A display panel, a method for manufacturing the display panel and a display device are provided. The display panel includes a base, a functional film layer, and a plurality of first light-emitting elements. The functional film layer includes a power source signal line layer, a data line layer and a compensation functional layer, the power source signal line layer includes a power source signal line pattern arranged at each subpixel region, the data line layer includes a data line pattern arranged at each subpixel region, and the compensation functional layer includes a compensation functional pattern arranged at at least one subpixel region. The first light-emitting element includes a first anode, a first light-emitting pattern and a first cathode sequentially laminated.

First claim

What is claimed is:

1. A display panel, comprising a base, a functional film layer arranged on the base, a plurality of first light-emitting elements arranged at a side of the functional film layer distal to the base, and a plurality of subpixel regions arranged in an array form, wherein
the functional film layer comprises a power source signal line layer, a data line layer and a compensation functional layer, the power source signal line layer comprises a power source signal line pattern arranged at each subpixel region, the data line layer comprises a data line pattern arranged at each subpixel region, the power source signal line pattern comprises a first portion extending in a first direction, the data line pattern extends in the first direction, and the compensation functional layer comprises a compensation functional pattern arranged at at least one subpixel region;
each of the first light-emitting elements comprises a first anode, a first light-emitting pattern and a first cathode sequentially laminated in a direction away from the base; an orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding power source signal line pattern onto the base at a first overlapping region, the orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding data line pattern onto the base at a second overlapping region, and the orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding compensation functional pattern onto the base at a third overlapping region; and the second overlapping region is arranged between the first overlapping region and the third overlapping region,
wherein in a direction perpendicular to the base, a difference between a thickness of the compensation functional layer and a thickness of the power source signal line layer is within a threshold range, or a difference between the thickness of the compensation functional layer and a thickness of the data line layer is within a threshold range.

2. The display panel according to claim 1 , wherein the first anode comprises a first edge portion and a second edge portion arranged opposite to each other in a second direction crossing the first direction, and a first intermediate portion arranged between the first edge portion and the second edge portion; and
an orthogonal projection of the first edge portion onto the base comprises the first overlapping region, an orthogonal projection of the second edge portion onto the base comprises the third overlapping region, and an orthogonal projection of the first intermediate portion onto the base comprises the second overlapping region.

3. The display panel according to claim 2 , wherein the functional film layer further comprise a gate scanning line layer, an initialization signal line layer, a resetting signal line layer and a light-emission control signal line layer,
the gate scanning line layer comprises a gate scanning line pattern arranged at each subpixel region, the initialization signal line layer comprises an initialization signal line pattern arranged at each subpixel region, the resetting signal line layer comprises a resetting signal line pattern arranged at each subpixel region, the light-emission control signal line layer comprises a light-emission control signal line pattern arranged at each subpixel region, and the gate scanning line pattern, the initialization signal line pattern, the resetting signal line pattern and the light-emission control signal line pattern extend in a second direction crossing the first direction.

4. The display panel according to claim 3 , wherein
the first anode further comprises a third edge portion and a fourth edge portion arranged opposite to each other in the first direction, the first intermediate portion is arranged between the third edge portion and the fourth edge portion, the third edge portion is coupled to the first edge portion and the second edge portion, the fourth edge portion is coupled to the first edge portion and the second edge portion;
the orthogonal projection of the first intermediate portion onto the base overlaps an orthogonal projection of a corresponding gate scanning line pattern onto the base and an orthogonal projection of a corresponding resetting signal line pattern onto the base at a sixth overlapping region.

5. The display panel according to claim 4 , wherein the first anode comprises a body portion and a via-hole connection portion, the body portion comprises the first edge portion, the second edge portion, the third edge portion, the fourth edge portion and the first intermediate portion, and the body portion is a centrosymmetric pattern.

6. The display panel according to claim 2 , wherein the first intermediate portion is a centrosymmetric pattern, and the orthogonal projection of the first intermediate portion onto the base coincides with the orthogonal projection of the first light-emitting pattern onto the base.

7. The display panel according to claim 3 , wherein the display panel comprises a first metal layer, a second metal layer and a third metal layer;
the gate scanning line layer, the resetting signal line layer and the light-emission control signal line layer are arranged in the first metal layer;
the initialization signal line layer is arranged in the second metal layer;
the data line layer, the power source signal line layer and the compensation functional layer are arranged in the third metal layer;
the functional film layer further comprises a first insulation layer and a second insulation layer, the first insulation layer is arranged between the first metal layer and the second metal layer, and the second insulation layer is arranged between the second metal layer and the third metal layer.

8. The display panel according to claim 3 , wherein the compensation functional pattern is made of a conductive material and coupled to the initialization signal line pattern.

9. The display panel according to claim 8 , wherein the compensation functional pattern and the data line pattern are arranged in a same layer.

10. The display panel according to claim 3 , further comprising a plurality of subpixel driving circuitries, wherein a first part of the subpixel driving circuitries correspond to the first light-emitting elements respectively, each of the first part of the subpixel driving circuitries is configured to drive a corresponding first light-emitting element to emit light; the subpixel driving circuitry comprises a driving transistor, a first transistor, a second transistor, a fourth transistor and a storage capacitor;
a gate electrode of the first transistor is coupled to a corresponding gate scanning line pattern, a first electrode of the first transistor is coupled to a second electrode of the driving transistor, and a second electrode of the first transistor is coupled to a gate electrode of the driving transistor;
a gate electrode of the second transistor is coupled to a corresponding resetting signal line pattern, a first electrode of the second transistor is coupled to a corresponding initialization signal line pattern, and a second electrode of the second transistor is coupled to the gate electrode of the driving transistor;
a gate electrode of the fourth transistor is coupled to the corresponding gate scanning line pattern, a first electrode of the fourth transistor is coupled to a corresponding data line pattern, and a second electrode of the fourth transistor is coupled to a first electrode of the driving transistor;
the first electrode of the driving transistor is coupled to a corresponding power source signal line pattern, and the second electrode of the driving transistor

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Liu Tingliang
• Yang Huijuan
• Zhang Yi
• Lee Sangwon
• Wang Yu
• Huangfu Lujiang

Classifications

• H10K59/121

  characterised by the geometry or disposition of pixel elements · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/80515

  characterised by their shape · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title