Apparatus for correcting a mismatch, digital-to-analog converter system, transmitter, base station, mobile device and method for correcting a mismatch

Patent metadata

Field	Value
Publication number	US-12034450-B2
Application number	US-201917754308-A
Country	US
Kind code	B2
Filing date	Dec 27, 2019
Priority date	Dec 27, 2019
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution based on a second number of bits. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits to generate first modified bits, and a second processing circuit comprising a second filter to modify the second number of bits to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC, which is based on the first modified bits and the second modified bits.

First claim

What is claimed is:

1. An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, wherein the first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC, and wherein the second segment generates a second contribution to the analog output signal based on a second number of bits of the digital input word, the apparatus comprising:
an input configured to receive the digital input word;
a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits in order to generate first modified bits;
a second processing circuit for the second number of bits comprising a second filter configured to modify the second number of bits in order to generate second modified bits; and
an output configured to output a modified digital input word for the DAC, wherein the modified digital input word is based on the first modified bits and the second modified bits.

2. The apparatus of claim 1 , wherein the first processing circuit further comprises a first extraction circuit configured to extract the first number of bits from the digital input word and to supply the first number of bits to the first filter.

3. The apparatus of claim 1 , wherein the second processing circuit further comprises a second extraction circuit configured to extract the second number of bits from the digital input word and to supply the second number of bits to the second filter.

4. The apparatus of claim 1 , wherein filter coefficients of the first filter are based on a measured error of the first segment.

5. The apparatus of claim 1 , wherein filter coefficients of the second filter are based on a measured error of the second segment.

6. The apparatus of claim 1 , further comprising:
a combiner circuit configured to combine the first modified bits, the second modified bits and the digital input word in order to generate the modified digital input word.

7. The apparatus of claim 6 , wherein the combiner circuit comprises:
a first combiner sub-circuit configured to combine the first modified bits and the second modified bits in order to generate a digital correction word; and
a second combiner sub-circuit configured to combine the digital input word and the digital correction word in order to generate the modified digital input word.

8. The apparatus of claim 1 , further comprising:
a combiner circuit configured to combine the first modified bits and the second modified bits in order to generate the modified digital input word.

9. The apparatus of claim 6 , wherein the combiner circuit is further configured to generate the modified digital input word based on a signal not related to the digital input word.

10. The apparatus of claim 6 , further comprising:
a second combiner circuit coupled between the combiner circuit and the output, wherein the second combiner circuit is configured to modify the modified digital input word by combining the modified digital input word with a signal not related to the digital input word.

11. The apparatus of claim 1 , further comprising:
a second combiner circuit coupled between the input and each of the first processing circuit and the second processing circuit, wherein the second combiner circuit is configured to modify the digital input word by combining the digital input word with a signal not related to the digital input word.

12. The apparatus of claim 9 , wherein an amplitude of the signal is lower than a full scale of the DAC.

13. The apparatus of claim 12 , wherein the amplitude of the signal is less than 1% of the full scale of the DAC.

14. The apparatus of claim 9 , wherein the signal exhibits a frequency outside a frequency passband of the DAC.

15. The apparatus of claim 14 , wherein the frequency of the signal is below the frequency passband of the DAC.

16. The apparatus of claim 14 , wherein the frequency of the signal is at least one decade below the frequency passband of the DAC.

17. The apparatus of claim 9 , wherein the signal is a sinusoidal signal.

18. The apparatus of claim 1 , further comprising:
a third processing circuit for a third number of bits of the digital input word used by a third segment of the DAC for generating a third contribution to the analog output signal,
wherein the third processing circuit comprises a third filter configured to modify the third number of bits in order to generate third modified bits, and
wherein the modified digital input word is further based on the third modified bits.

19. The apparatus of claim 18 , wherein the third processing circuit further comprises a third extraction circuit configured to extract the third number of bits from the digital input word and provide the third number of bits to the third filter.

20. The apparatus of claim 18 , wherein filter coefficients of the third filter are based on a measured error of the third segment.

21. The apparatus of claim 18 , wherein the first combiner sub-circuit is configured to combine the first modified bits, the second modified bits and the third modified bits in order to generate the digital correction word.

22. The apparatus of claim 1 , further comprising:
a filter adaptation circuit configured to determine respective filter coefficients for the first filter and the second filter based on measured errors of the first segment and the second segment.

23. A Digital-to-Analog Converter, DAC, system, comprising:
the apparatus according to claim 1 ; and
a DAC coupled to the output of the apparatus.

24. A transmitter, comprising:
a digital-to-analog converter system according to claim 23 ; and
a digital circuit configured to supply the digital input word to the input.

25. A method for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, wherein the first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC, and wherein the second segment generates a second contribution to the analog output signal based on a second number of bits of the digital input word, the method comprising:
receiving the digital input word;
modifying the first number of bits in order to generate first modified bits using a first filter in a first processing circuit for the first number of bits;
modifying the second number of bits in order to generate second modified bits using a second filter in a second processing circuit for the second number of bits; and
outputting a modified digital input word for the DAC, wherein the modified digital input word is based on the first modified bits and the second modified bits.

Assignees

• Intel Corp

Inventors

• Gruber Daniel
• Sanchez Ramon
• Azadet Kameran
• Clara Martin

Classifications

• H03M1/0626

  by filtering · CPC title

• H03M1/0639

  using dither, e.g. using triangular or sawtooth waveforms (for increasing resolution H03M1/201) · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03M1/1033 Primary

  over the full range of the converter, e.g. for correcting differential non-linearity · CPC title

• H03M1/1038 Primary

  by storing corrected or correction values in one or more digital look-up tables (H03M1/1057 takes precedence) · CPC title