Photoelectric conversion apparatus having avalanche photodiode
US-2023117198-A1 · Apr 20, 2023 · US
US12034017B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12034017-B2 |
| Application number | US-202318134084-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 13, 2023 |
| Priority date | Apr 8, 2019 |
| Publication date | Jul 9, 2024 |
| Grant date | Jul 9, 2024 |
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A sensor chip and an electronic device with SPAD pixels each including an avalanche photodiode element. The sensor chip includes a pixel area having an array of pixels, an avalanche photodiode element that amplifies a carrier by a high electric field area provided for the each of the pixels, an inter-pixel separation section that insulates and separates each of the pixels from adjacent pixels, and a wiring in a wiring layer laminated on a surface opposite to a light receiving surface of the semiconductor substrate that covers at least the high electric field area. The pixel array includes a dummy pixel area located near a peripheral edge of the pixel area. A cathode and an anode electric potential of the avalanche photodiode element arranged in the dummy pixel area are the same, or at least one of the cathode and anode electric potential is in a floating state.
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What is claimed is: 1. A sensor chip, comprising: a pixel array section, wherein the pixel array section includes a pixel area in which a plurality of pixels is arranged in rows and columns, wherein each pixel in the plurality of pixels includes an avalanche photodiode element, wherein the pixel area includes a dummy pixel area and a reference pixel area, wherein the dummy pixel area includes a plurality of dummy pixels, and wherein, for each dummy pixel in the plurality of dummy pixels, at least one of a cathode electric potential of the avalanche photodiode element and an anode electric potential of the avalanche photodiode element is in a floating state. 2. The sensor chip according to claim 1 , wherein the dummy pixel area is located near a peripheral edge of the pixel area. 3. The sensor chip according to claim 1 , wherein the dummy pixel area surrounds the reference pixel area. 4. The sensor chip according to claim 1 , wherein the reference pixel area includes a plurality of reference pixels. 5. The sensor chip according to claim 4 , wherein, for each dummy pixel in the plurality of dummy pixels, a cathode and an anode of the avalanche photodiode element are short-circuited. 6. The sensor chip according to claim 1 , wherein, for each reference pixel in the plurality of reference pixels, the avalanche photodiode element amplifies a carrier. 7. The sensor chip according to claim 1 , wherein, for each pixel in the plurality of pixels, the avalanche photodiode includes an avalanche multiplying area. 8. The sensor chip according to claim 7 , further comprising: for each pixel in the plurality of pixels, a wiring that is included in a sensor-side wiring layer and that is more widely formed than the avalanche multiplying area of the avalanche photodiode element. 9. The sensor chip according to claim 8 , wherein the wiring is metal. 10. The sensor chip according to claim 9 , wherein the wiring covers the avalanche multiplying area. 11. The sensor chip according to claim 10 , wherein the wiring is reflective. 12. The sensor chip according to claim 1 , wherein anodes of the avalanche photodiode elements of the reference pixels are coupled to one another by a common wiring. 13. The sensor chip according to claim 12 , wherein anodes of the avalanche photodiode elements of the dummy pixels are coupled to one another by a common wiring. 14. The sensor chip according to claim 13 , wherein the anodes of the reference pixels and the anodes of the dummy pixels are separated from each other. 15. The sensor chip according to claim 1 , wherein each of the reference pixels includes: a quenching resistance coupled to the avalanche photodiode element; and an inverter that outputs a received light signal on a basis of electrons having been multiplied in the avalanche photodiode element, and wherein a quenching resistance is not coupled to the avalanche photodiode element of any of the dummy pixels. 16. The sensor chip according to claim 1 , further comprising: an inter-pixel separation section, wherein, for each pixel in the plurality of pixels, the inter-pixel separation section insulates and separates the pixel from another pixel adjacent to the pixel in a semiconductor substrate in which the avalanche photodiode is formed. 17. The sensor chip according to claim 16 , wherein the inter-pixel separation section is embedded in the semiconductor substrate. 18. The sensor chip according to claim 17 , wherein the inter-pixel separation section includes a metal film covered by an insulating film. 19. The sensor chip according to claim 16 , wherein the inter-pixel separation section is reflective. 20. An electronic device, comprising: an optical system; a pixel array section, wherein the pixel array section includes a pixel area in which a plurality of pixels is arranged in rows and columns, wherein each pixel in the plurality of pixels includes an avalanche photodiode element, wherein the pixel array section includes a dummy pixel area and a reference pixel area, wherein the dummy pixel area includes a plurality of dummy pixels, and wherein, for each dummy pixel in the plurality of dummy pixels, at least one of a cathode electric potential of the avalanche photodiode element and an anode electric potential of the avalanche photodiode element is in a floating state; and an image processing circuit, wherein the optical system guides image light to the pixel array section, and wherein the image processing circuit performs image processing for building up a distance image.
the potential barrier working in avalanche mode, e.g. avalanche photodiodes · CPC title
Interconnections · CPC title
Pixel isolation structures · CPC title
Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title
Reflectors · CPC title
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