Semiconductor packages including at least one die position checker

Patent metadata

Field	Value
Publication number	US-12033952-B2
Application number	US-202318450143-A
Country	US
Kind code	B2
Filing date	Aug 15, 2023
Priority date	Jul 29, 2020
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

A semiconductor package may include a first die disposed on a package substrate, a second die stacked on the first die, and a first position checker disposed on the package substrate. The first position checker may indicate a first position allowable range in which a first side of the first die can be located.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first die disposed on a package substrate;
a second die stacked on the first die;
a third die stacked on the second die; and
first, second, and third position checkers disposed on the package substrate,
wherein in order to indicate a first position allowable range in which a first side of the first die can be located, the first position checker comprises:
a first reference pattern indicating a first reference position where the first side of the first die is to be located; and
a first limit pattern spaced apart from the first reference pattern by the first position allowable range, and
wherein in order to indicate a second position allowable range in which a second side of the second die can be located, the second position checker comprises:
a second reference pattern indicating a second reference position where the second side of the second die is to be located; and
a second upper limit pattern and a second lower limit pattern that are spaced apart from each other with the second reference pattern therebetween.

2. The semiconductor package of claim 1 , wherein the first limit pattern and the second lower limit pattern are disposed to face each other between the first reference pattern and the second reference pattern.

3. The semiconductor package of claim 1 , wherein the first limit pattern and the second lower limit pattern have line shapes extending substantially in parallel.

4. The semiconductor package of claim 1 , wherein the first reference pattern and the second reference pattern have substantially the same shape, and the first limit pattern, the second upper limit pattern and the second lower limit pattern have substantially the same shape.

5. The semiconductor package of claim 1 , wherein the first reference pattern has a line shape, and the first limit pattern has a dotted shape substantially parallel to the line shape.

6. The semiconductor package of claim 1 , further comprising a first fiducial mark and a second fiducial mark disposed on the package substrate.

7. The semiconductor package of claim 1 , wherein the second upper limit pattern is spaced apart from the second lower limit pattern by the second position allowable range.

8. The semiconductor package of claim 7 , wherein the second upper limit pattern and the second lower limit pattern are spaced apart from the second reference pattern by substantially the same distance.

9. The semiconductor package of claim 1 , wherein the second reference pattern has a line shape, and each of the second upper limit pattern and the second lower limit pattern has a dotted line shape substantially parallel to the line shape.

10. The semiconductor package of claim 1 , wherein the third position checker has substantially the same shape as the first position checker.

11. The semiconductor package of claim 1 , wherein in order to indicate a third position allowable range in which a third side of the third die can be located, the third position checker comprises:
a third reference pattern indicating a third reference position where the third side of the third die is to be located; and
a third limit pattern spaced apart from the third reference pattern by the third position allowable range.

12. The semiconductor package of claim 1 , wherein the second die is offset stacked from the first die to expose a portion of the first die, adjacent to the first side of the first die outside the second side, and
wherein the third die is offset stacked from the second die to expose a portion of the second die, adjacent to the second side of the second die outside the third side.

13. The semiconductor package of claim 12 , wherein the first die further comprises bonding pads, and
wherein the package substrate further comprises bonding fingers connected to the bonding pads by bonding wires.

Assignees

• Sk Hynix Inc

Inventors

• Min Bok Gyu
• Lee Suk Won

Classifications

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title