Method for resetting an array of resistive memory cells

Patent metadata

Field	Value
Publication number	US-12033698-B2
Application number	US-202017782446-A
Country	US
Kind code	B2
Filing date	Dec 3, 2020
Priority date	Dec 4, 2019
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

A method for resetting an array of Resistive Memory cells by applying a sequence of N reset operations, each reset operation including the application of a reset technique, the method including, at the first reset operation, performing the first reset operation by applying the reset technique having the highest relative correction yield; at the j-th reset operation of the N−1 subsequent reset operations, j being an integer number between 2 and N, defining a reset technique to be used at the j-th reset operation and performing the j-th reset operation.

First claim

The invention claimed is:

1. A method for resetting an array of Resistive Memory cells, that is for putting at least one cell of the array of Resistive Memory cells in its high resistive state, by applying a sequence of N reset operations, each reset operation comprising application of a reset technique, said method comprising:
at a first reset operation, performing the first reset operation by applying the reset technique having the highest relative correction yield;
at a j-th reset operation of the N−1 subsequent reset operations, j being an integer number comprised between 2 and N, defining a reset technique to be used at the j-th reset operation and performing the j-th reset operation;
the relative programming yield for the array of Resistive Memory cells to be reset being measured prior to the first reset operation by performing N reset operation and measuring after each reset operation the resistance of the High-Resistive State of each cell.

2. The method according to claim 1 , wherein the reset technique is chosen among a set of techniques comprising: reprogramming, applying voltage pulses with increasing amplitudes, applying voltage pulses with increasing temporal duration, applying voltage pulses with the same features.

3. The method according to claim 1 , wherein the number N of reset operations is comprised between 1 and 9.

4. The method according to claim 1 , wherein the reset technique to be used at the j-th reset operation is the reset technique having the highest relative correction yield at the j-th reset operation.

5. The method according to claim 1 , wherein the reset technique to be used at the j-th reset operation is the reset technique having a highest relative correction yield among the values of the relative correction yield that have not yet been used prior to the j-th reset operation.

6. The method according to claim 2 , wherein the reprogramming reset technique comprises a step of set the array of Resistive Memory cells followed by a step of reset of the array of Resistive Memory cells.

7. The method according to claim 2 , wherein when applying voltage pulses with increasing amplitudes, the increase step is comprised between 50 mV and 1 V.

8. The method according to claim 2 , wherein when applying voltage pulses with increased temporal duration, a temporal width is increased by a decade.

Assignees

• Commissariat Energie Atomique
• Weebit Nano Ltd

Inventors

• Molas Gabriel
• Bricalli Alessandro
• Piccolboni Guiseppe
• Regev Amir

Classifications

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0033

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C13/0097 Primary

  Erasing, e.g. resetting, circuits or methods · CPC title