Display panel, gate drive circuit and driving method thereof

Patent metadata

Field	Value
Publication number	US-12033586-B2
Application number	US-202218273041-A
Country	US
Kind code	B2
Filing date	Aug 23, 2022
Priority date	Sep 28, 2021
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

A display panel, a gate drive circuit and a driving method thereof. The gate drive circuit includes drive units. A first cascaded input end OUT(n−1) of a first shift register (100) of each of the drive units is connected to a different start signal end STV; a plurality of drive units in the drive units include a reset control sub-circuit (9), where the reset control sub-circuit (9) is connected with a second cascaded input end OUT(n+1) of a last shift register (100) and one or more start signal ends STV, and is configured to control an electric potential of the second cascaded input end OUT(n−1) according to an electric potential of the one or more start signal ends STV.

First claim

The invention claimed is:

1. A gate drive circuit, comprising:
drive units, wherein each of the drive units comprises cascaded shift registers; wherein each of the shift registers comprises an input sub-circuit, a first reset sub-circuit and an output sub-circuit;
wherein the input sub-circuit is connected with a first cascaded input end and a first node, and is configured to control an electric potential of the first node under control of an electric potential of the first cascaded input end; the output sub-circuit is configured to control an electric potential of a signal output end under control of the electric potential of the first node; the first reset sub-circuit is connected with the first node and a second cascaded input end, and is configured to reset the first node under control of an electric potential of the second cascaded input end;
wherein the first cascaded input end of a first shift register of each of the drive units is connected to a different start signal end; one or more drive units in the drive units comprise a reset control sub-circuit, wherein the reset control sub-circuit is connected with the second cascaded input end of a last shift register and one or more start signal ends, and is configured to control an electric potential of the second cascaded input end of the last shift register according to an electric potential of the one or more start signal ends; the start signal end connected with the first cascaded input end of the first shift register in one of the one or more drive units is different from the one or more start signal ends connected with the reset control sub-circuit in the one of the one or more drive units.

2. The gate drive circuit according to claim 1 , wherein the reset control sub-circuit comprises:
one or more first transistors, wherein both a control electrode and a first electrode of a first transistor are connected to a same start signal end, and a second electrode of the first transistor is connected to the second cascaded input end of the last shift register.

3. The gate drive circuit according to claim 1 , wherein the input sub-circuit comprises:
a second transistor, wherein a control electrode of the second transistor is connected to the first cascaded input end, a first electrode of the second transistor is connected to a first scan signal end, and a second electrode of the second transistor is connected to the first node.

4. The gate drive circuit according to claim 1 , wherein the first reset sub-circuit comprises:
a third transistor, wherein a control electrode of the third transistor is connected to the second cascaded input end, a first electrode of the third transistor is connected to a second scan signal end, and a second electrode of the third transistor is connected to the first node.

5. The gate drive circuit according to claim 1 , wherein the output sub-circuit comprises:
a fourth transistor, wherein a control electrode of the fourth transistor is connected to the first node, a first electrode of the fourth transistor is connected to a first clock signal end, and a second electrode of the fourth transistor is connected to the signal output end.

6. The gate drive circuit according to claim 5 , wherein the output sub-circuit further comprises:
a bootstrap capacitor, wherein a first electrode of the bootstrap capacitor is connected to the first node, and a second electrode of the bootstrap capacitor is connected to the second electrode of the fourth transistor.

7. The gate drive circuit according to claim 1 , wherein a shift register further comprises:
a pull-down control sub-circuit connected with a second clock signal end and a second node, and configured to control an electric potential of the second node according to an electric potential of the second clock signal end; and
a pull-down sub-circuit connected with the second node, the signal output end and a power signal end, and configured to control the signal output end to be connected to the power signal end under control of the electric potential of the second node.

8. The gate drive circuit according to claim 7 , wherein the shift register further comprises:
a storage sub-circuit connected to the second node, and configured to maintain the electric potential of the second node.

9. The gate drive circuit according to claim 8 , wherein the pull-down control sub-circuit comprises a fifth transistor, wherein both a control electrode and a first electrode of the fifth transistor are connected with the second clock signal end, and a second electrode of the fifth transistor is connected to the second node;
the pull-down sub-circuit comprises a sixth transistor, wherein a control electrode of the sixth transistor is connected with the second node, a first electrode of the sixth transistor is connected with the power signal end, and a second electrode of the sixth transistor is connected to the signal output end; and
the storage sub-circuit comprises a storage capacitor, wherein a first electrode of the storage capacitor is connected with the power signal end, and a second electrode of the storage capacitor is connected with the second node.

10. The gate drive circuit according to claim 7 , wherein the shift register further comprises:
a noise-control sub-circuit connected with the first node, the second node and the power signal end, configured to control the second node to be connected to the power signal end under control of the electric potential of the first node, and control the first node to be connected to the power signal end under control of the electric potential of the second node.

11. The gate drive circuit according to claim 10 , wherein the noise-control sub-circuit comprises:
a seventh transistor, wherein a control electrode of the seventh transistor is connected to the second node, a first electrode of the seventh transistor is connected to the power signal end, and a second electrode of the seventh transistor is connected to the first node; and
an eighth transistor, wherein a control electrode of the eighth transistor is connected to the first node, a first electrode of the eighth transistor is connected to the power signal end, and a second electrode of the eighth transistor is connected to the second node.

12. The gate drive circuit according to claim 1 , wherein a shift register further comprises:
a second reset sub-circuit connected with the first node, a power signal end and a reset signal end, and configured to control the first node to be connected to the power signal end under control of the reset signal end.

13. The gate drive circuit according to claim 12 , wherein the second reset sub-circuit comprises:
a ninth transistor, wherein a control electrode of the ninth transistor is connected to the reset signal end, a first electrode of the ninth transistor is connected to the power signal end, and a second electrode of the ninth transistor is connected to the second node.

14. A display panel, comprising the gate drive circuit according to claim 1 .

15. A driving method of a gate drive circuit, wherein the driving method is applied to the gate drive circuit according to claim 1 , and the driving method comprises:
for the last shift register,
driving the input sub-circuit to control the electric potential of the first node under control of the electric potential of the first cascaded input end;
driving the output sub-circuit to control the electric potential of the signal output end under control of the electric potential of the first node;
driving the reset control sub-circuit to control the electric potential of the second cascaded input end of the last sh

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zong Shaolei
• Sun Wei
• Liu Rui
• Sun Jigang
• Peng Kuanjun

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title