Shift register in display, gate drive circuit, display device, and driving method for same

Patent metadata

Field	Value
Publication number	US-12033554-B2
Application number	US-202117627143-A
Country	US
Kind code	B2
Filing date	Apr 12, 2021
Priority date	May 14, 2020
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

A shift register, a gate drive circuit, a display device, and a driving method for the same. The shift register comprises a first output sub-circuit, which provides, under control of an INPUT or a RESET, a signal of a CN or a CNB to a pull-up node, outputs, according to a voltage level of the pull-up node, a signal of a CK to an OUT, transmits, under control of a CKB, a CKB to a pull-down node, and pulls down, according to a voltage level of the pull-down node, a voltage level of the OUT; a second output sub-circuit, which outputs, during a scan output stage and under control of a GON, a signal of the OUT to a GOUT; and a transfer sub-circuit, which pulls down, during a scan transfer stage and under control of a GOFF, a voltage level of the GOUT.

First claim

The invention claimed is:

1. A shift register, comprising: a first output sub-circuit, a second output sub-circuit and a transfer sub-circuit, wherein the shift register comprises a signal output terminal and a line output terminal, the signal output terminal being connected with the first output sub-circuit and the second output sub-circuit, and the line output terminal being connected with the second sub-circuit and the transfer sub-circuit; wherein the line output terminal is connected with a pixel line, and the signal output terminal is not connected with the pixel line, only transfer and reset of shift register is performed;
the first output sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-up node under control of a signal input terminal or a reset terminal, and output a signal of a first clock signal terminal to the signal output terminal according to a level of the pull-up node; transmit a signal of a second clock signal terminal to a pull-down node under control of the second clock signal terminal, and pull down a level of the signal output terminal according to a level of the pull-down node;
wherein the shift register is adapted to a visuosensory area with a plurality of scanning lines and a non-visuosensory area with a plurality of scanning lines; the second output sub-circuit is configured to output a signal of the signal output terminal to the line output terminal under control of a line-ON enable signal at a scanning output stage of the visuosensory area and a scanning output stage of the non-visuosensory area; and
the transfer sub-circuit is configured to pull down a level of the line output terminal under control of a line-OFF enable signal at a scanning transfer stage of the visuosensory area and a scanning transfer stage of the non-visuosensory area;
wherein the second output sub-circuit comprises a first transistor, a control electrode of the first transistor being connected with the line-ON enable terminal, a first electrode of the first transistor being connected with the signal output terminal, and a second electrode of the first transistor being connected with the line output terminal; and
wherein the transfer sub-circuit comprises a second transistor, a control electrode of the second transistor being connected with the line-OFF enable terminal, a first electrode of the second transistor being connected with a third power supply terminal, and a second electrode of the second transistor being connected with the line output terminal;
wherein the first output sub-circuit comprises an input sub-circuit, and an intermediate output sub-circuit, the input sub-circuit being configured to provide the signal of the first power supply terminal to the pull-up node under control of the signal input terminal, and the intermediate output sub-circuit being configured to output the signal of the first clock signal terminal to the signal output terminal according to the level of the pull-up node;
wherein the intermediate output sub-circuit comprises a fifth transistor and a first capacitor, wherein:
a control electrode of the fifth transistor is connected with the pull-up node, a first electrode of the fifth transistor is connected with the first clock signal terminal, and a second electrode of the fifth transistor is connected with the signal output terminal;
one terminal of the first capacitor is connected with the pull-up node, and the other terminal of the first capacitor is connected with the signal output terminal.

2. The shift register according to claim 1 , wherein a frequency of an input signal of the first clock signal terminal and a frequency of an input signal of the second clock signal terminal of the first output sub-circuit at the scanning transfer stage are the same; a frequency of an input signal of the first clock signal terminal and a frequency of an input signal of the second clock signal terminal of the first output sub-circuit at the scanning output stage are the same, and the frequency of the input signal of the first clock signal terminal or the frequency of the input signal of the second clock signal terminal at the scanning output stage is less than the frequency of the input signal of the first clock signal terminal or the frequency of the input signal of the second clock signal terminal at the scanning transfer stage.

3. A gate drive circuit, comprising a plurality of cascaded shift registers according to claim 2 .

4. The shift register according to claim 1 , wherein the first output sub-circuit further comprises a first reset sub-circuit, a pull-down sub-circuit, a pull-down control sub-circuit, and a second reset sub-circuit, and wherein:
the first reset sub-circuit is configured to provide the signal of the second power supply terminal to the pull-up node under control of the reset terminal;
the pull-down control sub-circuit is configured to pull down the level of the pull-down node according to the level of the pull-up node; transmit the signal of the second clock signal terminal to the pull-down node under control of the second clock signal terminal, and pull down the level of the pull-up node according to the level of the pull-down node;
the pull-down sub-circuit is configured to pull down the level of the pull-down node according to the level of the signal output terminal; pull down the level of the signal output terminal according to the level of the pull-down node; and
the second reset sub-circuit is configured to reset the pull-up node under control of a total reset terminal.

5. The shift register according to claim 4 , wherein the second reset sub-circuit comprises a sixth transistor, and wherein:
a control electrode of the sixth transistor is connected with the total reset terminal, a first electrode of the sixth transistor is connected with a third power supply terminal, and a second electrode of the sixth transistor is connected with the pull-up node.

6. The shift register according to claim 4 , wherein the pull-down control sub-circuit comprises: a seventh transistor, an eighth transistor, and a ninth transistor, and the pull-down sub-circuit comprises: a tenth transistor, an eleventh transistor, and a second capacitor, and wherein:
a control electrode of the seventh transistor is connected with the pull-down node, a first electrode of the seventh transistor is connected with a third power supply terminal, and a second electrode of the seventh transistor is connected with the pull-up node;
a control electrode of the eighth transistor is connected with the pull-up node, a first electrode of the eighth transistor is connected with the third power supply terminal, and a second electrode of the eighth transistor is connected with the pull-down node;
both a control electrode and a first electrode of the ninth transistor are connected with the second clock signal terminal, and a second electrode of the ninth transistor is connected with the pull-down node;
a control electrode of the tenth transistor is connected with the pull-down node, a first electrode of the tenth transistor is connected with the third power supply terminal, a second electrode of the tenth transistor is connected with the signal output terminal;
a control electrode of the eleventh transistor is connected with the signal output terminal, a first electrode of the eleventh transistor is connected with the third power supply terminal, and a second electrode of the eleventh transistor is connected with the pull-down node; and
one terminal of the second capacitor is connected with the third power supply terminal, and the other terminal of the second capacitor is connected with the pull-down node.

7. The shift register according to claim 1 , wherein the input sub-circuit comprises: a third t

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zong Shaolei
• Sun Jigang
• Kung Chingwen
• Sun Wei

Classifications

• G09G3/3674 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2354/00

  Aspects of interface with display user · CPC title

• G09G3/2092

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title