Integrated assemblies and methods of forming integrated assemblies

Patent metadata

Field	Value
Publication number	US-12029032-B2
Application number	US-202318117989-A
Country	US
Kind code	B2
Filing date	Mar 6, 2023
Priority date	Nov 23, 2015
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

First claim

We claim:

1. An integrated assembly, comprising:
a first channel structure extending substantially vertically;
a second channel structure extending substantially vertically;
a stack of insulating materials comprising a lower tier of a first insulating material, a higher tier of the first insulating material and an intermediate tier of a second insulating material;
a gating structure extending within the stack of insulating materials between the first channel structure and the second channel structure and having a first gating region extending along the first channel structure, a second gating region extending along the second channel structure, and an interconnecting region extending laterally between the first and second gating regions;
a first etch-resistant material over the gating structure;
a second etch-resistant material extending laterally between the first and second gating regions; and
first and second conductive structures extending through the first etch-resistant material, the first conductive structure being over the first channel structure and the second conductive structure being over the second channel structure.

2. The integrated assembly of claim 1 wherein the first etch-resistant material comprises one or more members of the group consisting of HfO, ZiO and AlO.

3. The integrated assembly of claim 1 wherein the second etch resistant material is disposed beneath the interconnecting region.

4. The integrated assembly of claim 1 wherein a first part of the gating structure and the first channel structure are incorporated into a select device electrically coupled in series with a plurality of memory cells.

5. The integrated assembly of claim 4 wherein memory cells comprised by the plurality of memory cells are vertically-stacked over the select device.

6. The integrated assembly of claim 1 wherein the first and second channel structures are supported by a semiconductor base having a substantially horizontal primary surface, and wherein the first and second channel structures extend primarily substantially orthogonally relative to the substantially horizontal primary surface.

7. The integrated assembly of claim 1 wherein bottom surfaces of the gating regions are along the lower tier of the first insulating material; a bottom surface of the interconnecting region being along the higher tier of the first insulating material; and the intermediate tier of the second insulating material is directly against side surfaces of the gating regions.

8. An integrated assembly, comprising:
vertically-stacked memory cells over a select device;
a first semiconductor channel material extending vertically through multiple memory cells comprised by the vertically-stacked memory cells;
a second semiconductor channel material comprised by the select device; and
a gating structure comprised by the select device, the gating structure being spaced from the second semiconductor channel material by a gate dielectric material, the gating structure having a gating region and an interconnecting region of a common and continuous material; the interconnecting region extending laterally outwardly from the gating region on a side opposite the second semiconductor channel region, and being narrower than a length of the gating region.

9. The integrated assembly of claim 8 wherein the interconnecting region of the gating structure is approximately centered relative to the length of the gating region.

10. The integrated assembly of claim 8 wherein the interconnecting region and the gating region are about the same thickness as one another.

11. The integrated assembly of claim 8 wherein the interconnecting region is thicker than the gating region.

12. The integrated assembly of claim 8 wherein a semiconductor material plug is between the first and second semiconductor channel materials.

13. The integrated assembly of claim 8 wherein the gating structure extends within a stack of alternating first and second insulating materials; a bottom surface of the gating region being along a lower tier of first insulative material; a bottom surface of the interconnecting region being along a higher tier of first insulative material; and an intermediate tier of second insulative material being between the lower and higher tiers of the first insulative material.

14. The integrated assembly of claim 13 wherein the first insulative material comprises silicon dioxide, and the second insulative material comprises a high-k oxide.

15. The integrated assembly of claim 8 wherein the common and continuous material comprises metal.

16. The integrated assembly of claim 8 wherein the second semiconductor channel material includes a ridge over an upper surface of the gating region.

17. The integrated assembly of claim 16 wherein a conductive plug is over and adjacent said ridge.

Assignees

• Micron Technology Inc

Inventors

• Dorhout Justin B
• Parekh Kunal R
• Roberts Martin C
• Akhtar Mohd Kamran
• Carter Chet E
• Daycock David

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P72/0418

  for etching · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P32/302

  Doping polycrystalline silicon or amorphous silicon layers · CPC title