DC-DC converter with selectable working mode

Patent metadata

Field	Value
Publication number	US-12027976-B2
Application number	US-202217683572-A
Country	US
Kind code	B2
Filing date	Mar 1, 2022
Priority date	Oct 15, 2021
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

A DC-DC converter circuit with selectable working modes is disclosed. Compared with the traditional chip that works in one mode, the DC-DC converter with selectable working modes adds only a mode selection circuit, so that the chip can work in voltage control mode or current control mode. On the one hand, the applications of the chip are more extensive, and on the other hand, when the applications are different, the cost of developing a DC-DC converter with selectable working mode is greatly reduced compared with the traditional DC-DC converter.

First claim

The invention claimed is:

1. A DC-DC converter circuit, comprising: a driving circuit, a current sensing circuit, an oscillator, a mode selection circuit, a pulse width modulator, a slope compensation circuit, an error amplifier, a compensation module, a first NMOS transistor, a second NMOS transistor, an inductor, a first capacitor, a first resistor, a second resistor, and a third resistor, wherein:
the driving circuit includes an input terminal and two output terminals,
the current sensing circuit includes four input terminals and an output terminal,
the slope compensation circuit includes three input ports and an output port,
the first NMOS transistor includes a drain connected to a first one of the input ports of the current sensing circuit and to an input current source, a source connected to a drain of the second NMOS transistor, a second one of the input ports of the current sensing circuit, and a first end of the inductor, and a gate connected to a first one of the output ports of the driving circuit,
a second one of the output ports of the driving circuit is connected to a gate of the second NMOS transistor,
the inductor, has a second end connected to a first terminal of the first capacitor, a first end of the first resistor, and a first end of the third resistor,
the first resistor has a second end connected to a first end of the second resistor,
the second NMOS transistor has a source connected to a second terminal of the first capacitor, a second end of the third resistor, and a second end of the second resistor,
the second end of the first resistor and the first end of the second resistor are connected to a first input terminal of the error amplifier,
the error amplifier has a second input terminal receiving a first reference voltage and an output terminal connected to a first input terminal of the pulse width modulator,
the pulse width modulator has an output terminal connected to the input terminal of the driving circuit,
the mode selection circuit has an input receiving a mode selection signal and an output connected to a third one of the input ports of the current sensing circuit and a first one of the input ports of the slope compensation circuit,
the output port of the current sensing circuit is connected to the slope compensation circuit,
the oscillator has an output connected to a second one of the input ports of the slope compensation circuit,
the output port of the slope compensation circuit is connected to a second input terminal of the pulse width modulator;
the compensation module includes a first operational amplifier, a first variable resistor, a second variable resistor, and a variable capacitor, and
the first operational amplifier has an output terminal, a first input terminal and a second input terminal, wherein the output terminal is connected to the first input terminal, the first input terminal and the second input terminal are respectively connected to first and second ends of the second variable resistor, the second input terminal is connected to a first end of the first variable resistor, a second end of the first variable resistor is connected to the variable capacitor and the first input terminal of the pulse width modulator, and the variable capacitor is grounded.

2. The DC-DC converter circuit as claimed in claim 1 , wherein the current sensing circuit includes a first bias current source, third through eighth NMOS transistors, first, second and third PMOS transistors, and a fourth resistor;
the first bias current source is connected to an internal power supply voltage and a drain of the third NMOS transistor,
a gate of the third NMOS transistor is the third one of the input ports of the current sensing circuit,
the third NMOS transistor has a source connected to a drain and a gate of the fourth NMOS transistor and a gate of each of the fifth and sixth NMOS transistors,
each of the fourth, fifth and sixth NMOS transistors has a source connected to ground,
the fifth NMOS transistor has a drain is connected to a drain and a gate of the first PMOS transistor and a gate of the second PMOS transistor,
the first PMOS transistor has a source connected to a source of the third PMOS transistor and a source of the seventh NMOS transistor,
gates of the seventh and eighth NMOS transistors are connected together as a fourth one of the input ports of the current sensing circuit,
the seventh NMOS transistor has a drain that is the first one of the input ports of the current sensing circuit,
the eighth NMOS transistor has a drain that is the second one of the input ports of the current sensing circuit and a source that is connected to a source of the second PMOS transistor,
the second PMOS transistor has a drain connected to a gate of the third PMOS transistor and a drain of the sixth NMOS transistor,
a drain of the third PMOS transistor is connected to a first end of the fourth resistor and is the output terminal of the current sensing circuit, and
a second end of the fourth resistor is grounded.

3. The DC-DC converter circuit as claimed in claim 1 , wherein the slope compensation circuit includes a second operational amplifier, a fifth resistor, fourth through sixth PMOS transistors, ninth through fourteenth NMOS transistors, and second and third capacitors;
the second operational amplifier has a first input terminal connected to a second reference voltage, a second input terminal connected to a first end of the fifth resistor and a source of the fourth PMOS transistor, and an output connected to a gate of the fourth PMOS transistor,
the fifth resistor has a second end connected to an input supply voltage,
a drain of the fourth PMOS transistor is connected to a gate and drain of the ninth NMOS transistor and gates of the tenth, eleventh and twelfth NMOS transistors,
the ninth NMOS transistor has a source connected to a drain of the tenth NMOS transistor,
the tenth NMOS transistor has a source that is grounded,
the eleventh NMOS transistor has a source connected to a drain of the twelfth NMOS transistor,
the twelfth NMOS transistor has a source that is grounded,
the eleventh NMOS transistor has a drain connected to a drain and a gate of the fifth PMOS transistor and a gate of the sixth PMOS transistor,
the fifth and sixth PMOS transistors each have a source connected to the internal power supply voltage,
the sixth PMOS transistor has a drain connected to a first terminal of the second capacitor and a drain of each of the thirteenth and fourteenth NMOS transistors,
the thirteenth NMOS transistor has a gate that is the first one of the input ports of the slope compensation circuit and a source connected to a first terminal of the third capacitor,
the second and third capacitors each have a second terminal connected to a source of the fourteenth NMOS transistor,
the second terminal of the second and third capacitors and the source of the fourteenth NMOS transistor are the third one of the input ports of the slope compensation circuit, and
the fourteenth NMOS transistor has a gate that is the second one of the input ports of the slope compensation circuit.

4. The DC-DC converter circuit as claimed in claim 1 , wherein the mode selection circuit includes: a sixth resistor, a diode, a first inverter, and a second inverter;
the sixth resistor has a first one end receiving the mode selection signal and a second end connected to an output of the diode, and an input of the first inverter,
the diode has an input connected to ground,
the first inverter has an output connected to an input of the second inverter, and
the second inverter has an output that is the output of the mode selection circuit.

5. The DC-DC converter circuit with selectable working modes as claimed in claim 1 , wherein the circuit of the variable resistor and the variable

Assignees

• Univ Electronic Sci & Tech China

Inventors

• Fan Hua
• Liu Yilin
• Yue Huichao
• Xu Kai
• Feng Quanyuan
• Su Huaying
• Wang Guosong

Classifications

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title

• H02M1/0025

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title