Semiconductor module and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12027517-B2
Application number	US-202217569040-A
Country	US
Kind code	B2
Filing date	Jan 5, 2022
Priority date	Jul 13, 2021
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

Disclosed is a semiconductor module including a substrate, a first semiconductor layer positioned on the substrate, an insulator positioned in a partial region on the first semiconductor layer, a second semiconductor layer positioned on the insulator, a first semiconductor device formed on the first semiconductor layer, and a second semiconductor device formed on the second semiconductor layer, wherein one of the first semiconductor layer and the second semiconductor layer includes gallium oxide (Ga 2 O 3 ) and the other includes silicon (Si).

First claim

The invention claimed is:

1. A semiconductor module, comprising:
a substrate,
a first semiconductor layer positioned on the substrate,
an insulator located in a partial region directly on the first semiconductor layer in a vertical direction,
a second semiconductor layer positioned directly on the insulator in a vertical direction,
a first semiconductor device formed on the first semiconductor layer; and
a second semiconductor device formed on the second semiconductor layer,
wherein one of the first semiconductor layer and the second semiconductor layer includes gallium oxide (Ga2O3) and the other of the first semiconductor layer and the second semiconductor layer includes silicon (Si); and
wherein the second semiconductor layer is positioned on the first semiconductor layer in a vertical direction; and
wherein the insulator is positioned between the first semiconductor layer and the second semiconductor layer in a vertical direction.

2. The semiconductor module of claim 1 , wherein the substrate comprises silicon (Si), silicon carbide (SiC), sapphire, gallium nitride (GaN), or gallium oxide (Ga2O3).

3. The semiconductor module of claim 1 , wherein the insulator comprises Al2O3, SiO2, or HfO2.

4. The semiconductor module of claim 1 , wherein a thickness of the insulator ranges about 10 nm to about 50 nm.

5. The semiconductor module of claim 1 , wherein the first semiconductor device comprises the first semiconductor layer, and an upper region of the first semiconductor layer is positioned on the first semiconductor layer; and the second semiconductor device comprises the second semiconductor layer, and an upper region of the second semiconductor layer is positioned on the second semiconductor layer.

6. The semiconductor module of claim 5 , wherein the first semiconductor layer upper region or the second semiconductor layer upper region comprises a metal layer, an insulating layer, or a combination thereof.

7. The semiconductor module of claim 1 , wherein the first semiconductor layer or the second semiconductor layer comprises a P-type region, an N-type region, or both regions in a partial region of the semiconductor layer.

8. The semiconductor module of claim 1 , wherein the first semiconductor layer or the second semiconductor layer is formed by stacking two or more epitaxial layers having different impurity concentrations.

9. The semiconductor module of claim 8 , wherein the first semiconductor layer or the second semiconductor layer is formed by stacking two or more layers selected from a buffer layer, an N-type epitaxial layer, an N−-type epitaxial layer, and an N+-type epitaxial layer.

10. The semiconductor module of claim 1 , wherein the first semiconductor device and the second semiconductor device are electrically connected by a wire or a metal line.

11. The semiconductor module of claim 1 , wherein the first semiconductor device comprises a control element, a temperature sensor, a current sensor, a protective circuit, or a combination thereof.

12. The semiconductor module of claim 11 , wherein the control element comprises an integrated circuit (IC) including a capacitor, a resistor, an inductor, a CMOS, a field effect transistor (MOSFET), a bipolar junction transistor (BJT), a diode, or a combination thereof.

13. The semiconductor module of claim 1 , wherein the second semiconductor device is a power semiconductor device.

14. The semiconductor module of claim 13 , wherein the second semiconductor device comprises a field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a bipolar junction transistor (BJT), a Schottky diode, a PN diode, or a combination thereof.

15. The semiconductor module of claim 1 , wherein the semiconductor module further comprises a protective layer covering the first semiconductor device and the second semiconductor device.

16. A method of manufacturing a semiconductor module, comprising:
forming a first semiconductor layer on a substrate;
forming an insulator in a partial region on the first semiconductor layer;
forming a second semiconductor layer on the insulator;
forming a first semiconductor device on the first semiconductor layer; and
forming a second semiconductor device on the second semiconductor layer;
wherein one of the first semiconductor layer and the second semiconductor layer comprises gallium oxide (Ga2O3) and the other comprises silicon (Si);
wherein forming the insulator and the second semiconductor layer comprises:
forming an insulator on the first semiconductor layer;
forming a first mask on a partial region of the insulator;
forming a second semiconductor layer on the insulator and the first mask;
removing the first mask and the second semiconductor layer formed on the first mask to expose the insulator;
forming a second mask on the second semiconductor layer; and
removing the exposed insulator and the second mask.

17. The method of claim 16 , wherein the method of manufacturing the semiconductor module further comprises forming a protective layer covering the first semiconductor device and the second semiconductor device.

18. The method of claim 17 , wherein the method of manufacturing the semiconductor module further comprises forming via holes from the upper end of the protective layer to the upper end of the first semiconductor device and the upper end of the second semiconductor device, respectively, and then filling the via holes with a metal to electrically connect the first semiconductor device and the second semiconductor device.

19. The method of claim 16 , wherein the method of manufacturing the semiconductor module further comprises electrically connecting the first semiconductor device and the second semiconductor device through a wire.

Assignees

• Hyundai Motor Co Ltd
• Kia Corp

Inventors

• Hong Jungyeop
• Chun Dae Hwan
• Joo Nackyong
• Jung Youngkyun
• Park Junghee

Classifications

• H10D62/80

  characterised by the materials · CPC title

• H10D30/60 Primary

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D10/421

  having both emitter-base and base-collector junctions ending at the same surface of the body · CPC title

• H10D84/08

  using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title