Steganography of hardware intellectual property

Patent metadata

Field	Value
Publication number	US-12026290-B2
Application number	US-202217589040-A
Country	US
Kind code	B2
Filing date	Jan 31, 2022
Priority date	Feb 5, 2021
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

In general, embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, and computing entities for modifying a design of a hardware IP. According to one embodiment, a method is provided, the method including generating a control and data flow graph (CDFG) representation for portions of the design. The method further includes partitioning the CDFG representation into a set of partitioned sub-graphs. The method further includes, for each partitioned sub-graph, generating a merged sub-graph to form a set of merged sub-graphs. Generating the merged sub-graph for each partitioned sub-graph involves generating a container sub-graph and merging the container sub-graph with the partitioned sub-graph to form the merged sub-graph. The container sub-graph may be a modification of the partitioned sub-graph with respect to an identified feature, in some examples. The method further includes synthesizing a modified design of the hardware IP including the set of merged sub-graphs.

First claim

That which is claimed:

1. A method for modifying a design of a hardware intellectual property (IP), the method comprising:
generating a control and data flow graph (CDFG) representation for each of one or more functions of the design;
partitioning the CDFG representation into a set of partitioned sub-graphs;
for each partitioned sub-graph, generating a merged sub-graph to form a set of merged sub-graphs based at least in part on:
performing an analysis on the partitioned sub-graph to identify at least one feature of one or more structural features and/or one or more functional features for the partitioned sub-graph,
generating a container sub-graph for the partitioned sub-graph based at least in part on the at least one feature, and
merging the partitioned sub-graph and the container sub-graph to generate the merged sub-graph; and

synthesizing a modified design of the hardware IP, the modified design comprising the set of merged sub-graphs.

2. The method of claim 1 , wherein partitioning the CDFG representation comprises using a partitioning algorithm configured to minimize cut edges of the set of partitioned sub-graphs.

3. The method of claim 1 , wherein the at least one feature comprises at least one of types of operations, a number of possible branches, or a number of constants and variables integrated in the partitioned sub-graph.

4. The method of claim 1 , wherein the container sub-graph comprises at least one of a randomly generated sub-graph, a modification of the partitioned sub-graph, or a sub-graph retrieved from a data storage.

5. The method of claim 1 , wherein merging the partitioned sub-graph and the container sub-graph is performed using a K-way graph merging algorithm.

6. The method of claim 1 , wherein merging the partitioned sub-graph and the container sub-graph is performed by implementing a key-based selector configured to control activation of functionality represented by the partitioned sub-graph or functionality represented by the container sub-graph.

7. The method of claim 1 , wherein merging the partitioned sub-graph and the container sub-graph is performed by implementing one or more derived keys, and functionality represented an end of the partitioned sub-graph regenerates the one or more derived keys based at least in part on an inserted key.

8. The method of claim 1 , wherein generating a merged sub-graph is further based at least in part on performing a data-path locking on the merged sub-graph.

9. The method of claim 8 , wherein performing the data-path locking on the merged CDFG sub-graph comprises adding a key dependency on at least one existing value so that the at least one existing value is restored only if a key is correctly applied.

10. An apparatus for modifying a design of a hardware intellectual property (IP), the apparatus comprising at least one processor and a memory comprising computer executable instructions, the memory and the computer executable instructions configured to, with the at least one processor, cause the apparatus to:
generate a control and data flow graph (CDFG) representation for each of one or more functions of the design;
partition the CDFG representation into a set of partitioned sub-graphs;
for each partitioned sub-graph, generate a merged sub-graph to form a set of merged sub-graphs based at least in part on:
perform an analysis on the partitioned sub-graph to identify at least one feature of one or more structural features and/or one or more functional features for the partitioned sub-graph,
generate a container sub-graph for the partitioned sub-graph based at least in part on the at least one feature, and
merge the partitioned sub-graph and the container sub-graph to generate the merged sub-graph; and

synthesize a modified design of the hardware IP, the modified design comprising the set of merged sub-graphs.

11. The apparatus of claim 10 , wherein partitioning the CDFG representation comprises using a partitioning algorithm configured to minimize cut edges of the set of partitioned sub-graphs.

12. The apparatus of claim 10 , wherein the at least one feature comprises at least one of types of operations, a number of possible branches, or a number of constants and variables integrated in the partitioned sub-graph.

13. The apparatus of claim 10 , wherein the container sub-graph comprises at least one of a randomly generated sub-graph, a modification of the partitioned sub-graph, or a sub-graph retrieved from a data storage.

14. The apparatus of claim 10 , wherein merging the partitioned sub-graph and the container sub-graph is performed using a K-way graph merging algorithm.

15. The apparatus of claim 10 , wherein merging the partitioned sub-graph and the container sub-graph is performed by implementing a key-based selector configured to control activation of functionality represented by the partitioned sub-graph or functionality represented by the container sub-graph.

16. The apparatus of claim 10 , wherein merging the partitioned sub-graph and the container sub-graph is performed by implementing one or more derived keys, and functionality represented an end of the partitioned sub-graph regenerates the one or more derived keys based at least in part on an inserted key.

17. The apparatus of claim 10 , wherein generating a merged sub-graph is further based at least in part on performing a data-path locking on the merged sub-graph.

18. The apparatus of claim 17 , wherein performing the data-path locking on the merged CDFG sub-graph comprises adding a key dependency on at least one existing value so that the at least one existing value is restored only if a key is correctly applied.

19. A computer program product for modifying a design of a hardware IP, the computer program product comprising at least one computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising executable portions configured to cause at least one processor to:
generate a control and data flow graph (CDFG) representation for each of one or more functions of the design;
partition the CDFG representation into a set of partitioned sub-graphs;
for each partitioned sub-graph, generate a merged sub-graph to form a set of merged sub-graphs based at least in part on:
perform an analysis on the partitioned sub-graph to identify at least one feature of one or more structural features and/or one or more functional features for the partitioned sub-graph,
generate a container sub-graph for the partitioned sub-graph based at least in part on the at least one feature, and
merge the partitioned sub-graph and the container sub-graph to generate the merged sub-graph; and

synthesize a modified design of the hardware IP, the modified design comprising the set of merged sub-graphs.

20. The computer program product of claim 19 , wherein partitioning the CDFG representation comprises using a partitioning algorithm configured to minimize cut edges of the set of partitioned sub-graphs.

Assignees

• Univ Florida

Inventors

• Bhunia Swarup
• Alaql Abdulrahman

Classifications

• G06F2115/08

  Intellectual property [IP] blocks or IP cores · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F2117/08

  HW-SW co-design, e.g. HW-SW partitioning · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F21/10

  Protecting distributed programs or content, e.g. vending or licensing of copyrighted material (protection in video systems or pay television H04N7/16) {; Digital rights management [DRM]} · CPC title