Microfluidic device for continuous ejection of fluids, in particular for ink printing, and related manufacturing process

US12023919B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12023919-B2
Application numberUS-202218064829-A
CountryUS
Kind codeB2
Filing dateDec 12, 2022
Priority dateMay 24, 2019
Publication dateJul 2, 2024
Grant dateJul 2, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A microfluidic device for continuous ejection of fluids includes: a semiconductor body that laterally delimits chambers; an intermediate structure which forms membranes each delimiting a top of a corresponding chamber; and a nozzle body which overlies the intermediate structure. The device includes, for each chamber: a corresponding piezoelectric actuator; a supply channel which traverses the intermediate structure and communicates with the chamber; and a nozzle which traverses the nozzle body and communicates with the supply channel. Each actuator is configured to operate i) in a resting condition such that the pressure of a fluid within the corresponding chamber causes the fluid to pass through the supply channel and become ejected from the nozzle as a continuous stream, and ii) in an active condition, where it causes a deformation of the corresponding membrane and a consequent variation of the pressure of the fluid, causing a temporary interruption of the continuous stream.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method, comprising: forming a piezoelectric actuator on a surface of a first dielectric layer of a first semiconductor wafer; forming a first protective layer on the piezoelectric actuator and on the surface of the first dielectric layer; forming a second protective layer on the first protective layer; forming a supply channel adjacent to the piezoelectric actuator and extending through the first protective layer, the second protective layer, and the first dielectric layer; forming a cavity in a second semiconductor wafer and extending through a first dielectric layer of the second semiconductor wafer and extending into a semiconductor layer of the second semiconductor wafer; forming a hole that extends entirely through the first dielectric layer and the semiconductor layer of the second semiconductor wafer; overlapping the hole of the second semiconductor wafer with the supply channel of the first semiconductor wafer by coupling the second semiconductor wafer to the first semiconductor wafer; forming a chamber in the first semiconductor wafer in fluid communication with the supply channel of the first semiconductor wafer, forming the chamber in the first semiconductor wafer including: forming a first portion with a first diameter; forming a second portion with a second diameter greater than the first diameter; and forming a connecting portion extending from the first portion to the second portion, the connecting portion having a width substantially equal to the first diameter. 2. The method according to claim 1 , wherein: forming the hole that extends entirely through the first dielectric layer and the semiconductor layer further includes forming the hole to a second dielectric layer of the second semiconductor wafer opposite to the first dielectric layer; and forming the chamber in the first semiconductor wafer further includes removing a portion of a semiconductor layer of the first semiconductor wafer spaced apart from the supply channel by a second dielectric layer of the first semiconductor wafer. 3. The method according to claim 2 , wherein forming the chamber in the first semiconductor wafer further includes: fluidically coupling the chamber in the semiconductor layer of the first semiconductor wafer to the supply channel in the first semiconductor wafer by removing a portion of the second dielectric layer of the first semiconductor wafer. 4. The method according to claim 2 , further comprising removing the second dielectric layer from the second semiconductor wafer opening an end of the hole furthest away from the supply channel. 5. The method according to claim 1 , wherein the hole has a third diameter less than the first diameter; and the supply channel has a fourth diameter that is substantially equal to the first diameter. 6. The method according to claim 1 , wherein forming the first portion further includes forming the first portion of the chamber in the first semiconductor wafer overlapping the supply channel in the first semiconductor wafer and overlapping the hole in the second semiconductor wafer. 7. The method according to claim 6 , wherein forming the second portion further includes forming the second portion of the chamber in the first semiconductor wafer overlapping the piezoelectric actuator of the first semiconductor wafer. 8. The method according to claim 1 , wherein: forming the hole in the second semiconductor wafer further includes forming the hole in the second semiconductor wafer with a third diameter; and forming the supply channel in the first semiconductor wafer further includes forming the supply channel in the first semiconductor wafer with a fourth diameter greater than the third diameter of the hole. 9. The method according to claim 8 , wherein the third diameter is less than the first diameter; and the fourth diameter is greater than the third diameter. 10. A method, comprising: forming a plurality of piezoelectric actuators on a surface of a first dielectric layer of a first semiconductor wafer; forming a first protective layer on the piezoelectric actuator and on the surface of the first dielectric layer; forming a second protective layer on the first protective layer; forming a plurality of supply channels adjacent to respective piezoelectric actuators of the plurality of piezoelectric actuators and extending through the first protective layer, the second protective layer, and the first dielectric layer of the first semiconductor wafer; forming a plurality of cavities in a second semiconductor wafer into a semiconductor layer of the second semiconductor wafer; forming a plurality of holes that extend into the second semiconductor wafer and entirely through the semiconductor layer of the second semiconductor wafer; overlapping each respective hole of the plurality of holes of the second semiconductor wafer with a corresponding supply channel of the plurality of supply channels of the first semiconductor wafer by coupling the second semiconductor wafer to the first semiconductor wafer; forming a plurality of chambers in the first semiconductor wafer in fluid communication with the plurality of supply channels of the first semiconductor wafer, wherein forming the plurality of chambers includes forming each respective chamber of the plurality of chambers to include: a first portion with a first diameter; a second portion with a second diameter greater than the first diameter; and a connecting portion extending from the first portion to the second portion, the connecting portion having a width substantially equal to the first diameter. 11. The method according to claim 10 , wherein the plurality of chambers including a first group of chambers and a second group of chambers, at least some respective first portions of the plurality of first portions of the first group of chambers are between adjacent first portions of the plurality of first portions of the second group of chambers. 12. The method according to claim 11 , wherein at least some respective first portions of the plurality of first portions of the second group of chambers are between adjacent first portions of the plurality of first portions of the first group of chambers. 13. The method according to claim 12 , wherein at least some respective second portions of the plurality of second portions of the second group of chambers are between adjacent second portions of the plurality of second portions of the first group of chambers. 14. The method according to claim 13 , wherein at least some respective second portions of the plurality of second portions of the first group of chambers are between adjacent second portions of the plurality of second portions of the second group of chambers. 15. The method according to claim 10 , wherein a first group of the plurality of holes are offset relative to a second group of the plurality of holes, the first group of the plurality of holes overlap a first group of chambers, and the second group of the plurality of holes overlap a second group of chambers. 16. The method of claim 10 , wherein each respective hole of the plurality of holes has a third diameter that is less than the first diameter; and each respective supply channel of the plurality of supply channels has a fourth diameter substantially equal to the first diameter. 17. The method of claim 10 , wherein the plurality of chambers including a first group of chambers and a second group of chambers offset from each other. 18. A method, comprising: forming a piezoelectric actuator on a first s

Assignees

Inventors

Classifications

  • Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00 · CPC title

  • Membrane type · CPC title

  • by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing · CPC title

  • Manufacturing print heads · CPC title

  • B41J2/03Primary

    by pressure · CPC title

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What does patent US12023919B2 cover?
A microfluidic device for continuous ejection of fluids includes: a semiconductor body that laterally delimits chambers; an intermediate structure which forms membranes each delimiting a top of a corresponding chamber; and a nozzle body which overlies the intermediate structure. The device includes, for each chamber: a corresponding piezoelectric actuator; a supply channel which traverses the i…
Who is the assignee on this patent?
St Microelectronics Srl
What technology area does this patent fall under?
Primary CPC classification B41J2/03. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Jul 02 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).