Compression engine with configurable search depths and window sizes

Patent metadata

Field	Value
Publication number	US-12021550-B2
Application number	US-202017119892-A
Country	US
Kind code	B2
Filing date	Dec 11, 2020
Priority date	Dec 11, 2020
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

Examples described herein relate to an encoder circuitry to apply one of multiple lossless data compression schemes on input data. In some examples, to compress input data, the encoder circuitry is to utilize a search window size and number of searches based on an applied compression scheme. In some examples, content of a memory is reconfigured to store data corresponding to a search window size of the applied compression scheme. In some examples, an applicable hash function is configured based on the applied compression scheme. In some examples, a number of searches are made for a byte position. In some examples, the encoder circuitry includes a hash table look-up and a bank decoder. In some examples, the hash table look-up is to generate a hash index to identify an address of an entry in the search window. In some examples, the bank decoder is to select a bank based on the hash index.

First claim

What is claimed is:

1. An apparatus comprising:
an encoder circuitry to apply one of multiple lossless data compression schemes on input data, wherein to compress input data, the encoder circuitry is to utilize a search window size and number of searches based on an applied compression scheme, wherein content of a memory is reconfigured to store data corresponding to a search window size of the applied compression scheme, and wherein an applicable hash function is configured based on the applied compression scheme.

2. The apparatus of claim 1 , wherein the number of searches comprises to a number of searches for a byte position.

3. The apparatus of claim 1 , wherein the encoder circuitry comprises a hash table look-up and a bank decoder, wherein:
the hash table look-up is to generate a hash index to identify an address of an entry in the search window and
the bank decoder is to select a bank based on the hash index.

4. The apparatus of claim 1 , wherein the lossless data compression schemes comprise Lempel Ziv-based encoding schemes based on one or more of: LZ77, LZ4, LZS, Zstandard, DEFLATE, Huffman coding, and Snappy standards.

5. The apparatus of claim 1 , wherein:
when the applied lossless data compression scheme is based on DEFLATE:
the search window size is 64 KB and
the number of searches is 16.

6. The apparatus of claim 1 , wherein:
when the applied lossless data compression scheme is based on Zstandard:
the search window size is 256 KB and
the number of searches is 64.

7. The apparatus of claim 1 , wherein the encoder circuitry is part of one or more of: a cryptographic accelerator, a central processing unit (CPU), a separate chip coupled to the CPU, a network interface, infrastructure processing unit (IPU), data processing unit (DPU), or smartNIC.

8. The apparatus of claim 1 , comprising: a network controller, wherein the network controller is to transmit the data encoded by the encoder circuitry.

9. The apparatus of claim 1 , comprising:
a server, rack, or datacenter coupled to the encoder circuitry, wherein the server, rack, or datacenter is to store data to be encoded by the encoder circuitry.

10. A method comprising:
configuring a memory to store input data corresponding to a search window size of an applied compression scheme and
applying one of multiple lossless data compression schemes on the input data by utilizing a search window size and number of searches based on the applied compression scheme.

11. The method of claim 10 , wherein the number of searches comprises to a number of searches for a byte position.

12. The method of claim 10 , comprising:
configuring a hash table look-up and bank decoder based on the applied compression scheme;
generating a hash index using the configured hash table look-up to identify an address of an entry in the search window; and
selecting a bank associated with the search window using the configured bank decoder based on the hash index.

13. The method of claim 10 , wherein the lossless data compression schemes comprise Lempel Ziv-based encoding schemes including one or more of: LZ77, LZ4, LZS, Zstandard, DEFLATE, Huffman coding, and Snappy standards and derivatives.

14. The method of claim 10 , wherein
when the applied lossless data compression scheme is DEFLATE:
the search window size is 64 KB and
the number of searches is 16.

15. The method of claim 10 , wherein
when the applied lossless data compression scheme is Zstandard:
the search window size is 256 KB and
the number of searches is 64.

16. The method of claim 10 , comprising applying one of multiple lossless data compression schemes on the input data in one or more of: a cryptographic accelerator, a central processing unit (CPU), a separate chip coupled to the CPU, or a network interface.

17. A non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
configure a memory to store input data corresponding to a search window size of an applied compression scheme and
apply one of multiple lossless data compression schemes on the input data by utilizing a search window size and number of searches based on the applied compression scheme.

18. The computer-readable medium of claim 17 , wherein the lossless data compression schemes comprise Lempel Ziv-based encoding schemes is based on one or more of: LZ77, LZ4, LZS, Zstandard, DEFLATE, Huffman coding, and Snappy standards.

19. The computer-readable medium of claim 17 , wherein
when the applied lossless data compression scheme is based on DEFLATE:
the search window size is 64 KB and
the number of searches is 16.

20. The computer-readable medium of claim 17 , wherein
when the applied lossless data compression scheme is based on Zstandard:
the search window size is 256 KB and
the number of searches is 64.

21. The computer-readable medium of claim 17 , wherein the one or more processors are part of one or more of: a cryptographic accelerator, a central processing unit (CPU), a separate chip coupled to the CPU, a network interface, infrastructure processing unit (IPU), data processing unit (DPU), or smartNIC.

Assignees

• Intel Corp

Inventors

• Kumar Smita
• Bissessur Sailesh
• Cassetti David K
• Palermo Stephen T

Classifications

• G06F16/2255

  Hash tables · CPC title

• H03M7/40

  Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code · CPC title

• H03M7/3084

  using adaptive string matching, e.g. the Lempel-Ziv method · CPC title

• H03M7/42

  using table look-up for the coding or decoding process, e.g. using read-only memory {(H03M7/4006 takes precedence)} · CPC title

• H03M7/3086 Primary

  employing a sliding window, e.g. LZ77 · CPC title