Systems and techniques for timing mismatch reduction

Patent metadata

Field	Value
Publication number	US-12021531-B2
Application number	US-202217895826-A
Country	US
Kind code	B2
Filing date	Aug 25, 2022
Priority date	Aug 25, 2022
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

Systems and techniques to offset conditions affecting propagation delay of a clock signal in a memory device. These include a device that includes a clock adjustment circuit, comprising a differential amplifier, an inverter coupled to a first output of the differential amplifier, and a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier. The swing oscillator driver includes a series of transistors, a signal path coupled to at least a first transistor of the series of transistors, wherein the signal path when in operation transmits a signal having a first voltage, and a strength control circuit coupled to the signal path, wherein the strength control circuit when in operation adjusts the first voltage of the signal to a second voltage.

First claim

What is claimed is:

1. A device, comprising:
a clock adjustment circuit comprising:
a differential amplifier;
an inverter coupled to a first output of the differential amplifier; and
a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier, wherein the swing oscillator driver comprises:
a series of transistors;
a signal path coupled to at least a first transistor of the series of transistors, wherein the signal path when in operation transmits a signal having a first voltage; and
a strength control circuit coupled to the signal path, wherein the strength control circuit when in operation adjusts the first voltage of the signal to a second voltage.

2. The device of claim 1 , comprising a feedback path coupled between the swing oscillator driver and the input of the differential amplifier.

3. The device of claim 2 , wherein the feedback path when in operation transmits the signal having the second voltage to the input of the differential amplifier.

4. The device of claim 1 , wherein the strength control circuit when in operation generates the second voltage of the signal to a first predetermined value.

5. The device of claim 4 , wherein the strength control circuit when in operation generates the second voltage of the signal to a second predetermined value.

6. The device of claim 5 , wherein the strength control circuit comprises a second transistor in parallel with a third transistor.

7. The device of claim 6 , wherein the strength control circuit when in operation generates the second voltage of the signal to the first predetermined value based on a first control input received at a first gate of the second transistor and a second control input received at a second gate of the third transistor.

8. The device of claim 7 , wherein the strength control circuit when in operation generates the second voltage of the signal to the second predetermined value based on a third control input received at the first gate of the second transistor and a fourth control input received at the second gate of the third transistor.

9. The device of claim 1 , wherein the clock adjustment circuit comprises:
a second differential amplifier;
a second inverter coupled to a third output of the second differential amplifier; and
a second swing oscillator driver coupled to a fourth output of the inverter and a second input of the second differential amplifier, wherein the second swing oscillator driver comprises:
a second series of transistors;
a second signal path coupled to at least a second transistor of the second series of transistors, wherein the second signal path when in operation transmits a second signal having a third voltage; and
a second strength control circuit coupled to the second signal path, wherein the second strength control circuit when in operation adjusts the third voltage of the second signal to a fourth voltage.

10. The device of claim 9 , wherein the second strength control circuit when in operation generates the fourth voltage of the second signal to a first predetermined value.

11. The device of claim 10 , wherein the second strength control circuit when in operation generates the fourth voltage of the second signal to a second predetermined value.

12. The device of claim 11 , wherein the second strength control circuit when in operation generates the fourth voltage of the second signal to the first predetermined value based on a first control input received at a first gate of a second transistor of the second strength control circuit and a second control input received at a second gate of a third transistor of the second strength control circuit.

13. The device of claim 12 , wherein the strength control circuit when in operation generates the fourth voltage of the second signal to the second predetermined value based on a third control input received at the first gate of the second transistor and a fourth control input received at the second gate of the third transistor.

14. A device, comprising:
a testing circuit comprising replica clock adjustment circuitry configured to replicate propagation of a clock signal by clock adjustment circuitry of the device within a first amount of time, wherein the replica clock adjustment circuitry comprises an oscillator, comprising:
a differential amplifier;
an inverter coupled to an output of the differential amplifier; and
a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier, wherein the swing oscillator driver comprises:
a signal path that when in operation transmits a signal having a first voltage; and
a strength control circuit coupled to the signal path, wherein the strength control circuit when in operation adjusts the first voltage of the signal to a second voltage.

15. The device of claim 14 , wherein the testing circuit comprises a counter coupled to the signal path, wherein the counter when in operation determines an oscillation cycle of the swing oscillator driver based upon a count of the counter.

16. The device of claim 15 , wherein the testing circuit comprises a register coupled to the counter.

17. The device of claim 16 , wherein the counter transmits the count to the register to be stored as an indication of a time corresponding to the oscillation cycle of the swing oscillator driver.

Assignees

• Micron Technology Inc

Inventors

• Morishita Yoshihito

Classifications

• H03K3/0315

  Ring oscillators · CPC title

• H03K3/014 Primary

  Modifications of generator to ensure starting of oscillations · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• H03K3/0232 Primary

  Monostable circuits · CPC title