Light-emitting diode chip having a gap between epitaxial structures and method for manufacturing the same, and display device

Patent metadata

Field	Value
Publication number	US-12021173-B2
Application number	US-202017435016-A
Country	US
Kind code	B2
Filing date	Nov 6, 2020
Priority date	Nov 6, 2020
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A light-emitting diode (LED) chip includes a plurality of epitaxial structures, at least one first electrode, and a plurality of second electrodes. Any two adjacent epitaxial structures of the plurality of epitaxial structures have a gap therebetween. Each epitaxial structure includes a first semiconductor pattern, a light-emitting pattern and a second semiconductor pattern stacked in sequence. First semiconductor patterns in at least two of the plurality of epitaxial structures are connected to each other to form a first semiconductor layer. A first electrode is electrically connected to the first semiconductor layer. Each second electrode is electrically connected to the second semiconductor pattern in at least one of the plurality of epitaxial structures.

First claim

What is claimed is:

1. A light-emitting diode (LED) chip, comprising:
a plurality of epitaxial structures, any two adjacent epitaxial structures of the plurality of epitaxial structures having a gap therebetween, each epitaxial structure including a first semiconductor pattern, a light-emitting pattern and a second semiconductor pattern stacked in sequence, and first semiconductor patterns in at least two of the plurality of epitaxial structures being connected to each other to form a first semiconductor layer;
at least one first electrode, a first electrode of the at least one first electrode being electrically connected to a respective first semiconductor layer; and
a plurality of second electrodes, each second electrode being electrically connected to the second semiconductor pattern in at least one of the plurality of epitaxial structures, wherein
the second semiconductor pattern is disposed independently; and
an orthographic projection of the first electrode of the at least one first electrode on a first plane is located within an orthographic projection of the respective first semiconductor layer electrically connected to the first electrode of the at least one first electrode on the first plane, and does not overlap with orthographic projections of the plurality of epitaxial structures on the first plane, the first plane being a plane parallel to the first semiconductor layer.

2. The LED chip according to claim 1 , wherein the at least one first electrode and the plurality of second electrodes are disposed on a same side of the first semiconductor layer.

3. The LED chip according to claim 1 , wherein an orthographic projection of the second electrode on the first plane at least partially overlaps with an orthographic projection of the second semiconductor pattern in the at least one epitaxial structure electrically connected to the second electrode on the first plane.

4. The LED chip according to claim 1 , wherein the plurality of epitaxial structures are arranged at intervals along a first direction, and the plurality of epitaxial structures extend along a second direction;
the first direction intersects the second direction.

5. The LED chip according to claim 4 , wherein a plurality of second semiconductor patterns in the plurality of epitaxial structures are arranged at intervals along the first direction, and the second semiconductor patterns extend along the second direction.

6. The LED chip according to claim 5 , wherein a plurality of light-emitting patterns in the plurality of epitaxial structures are arranged at intervals along the first direction, and the light-emitting patterns extend along the second direction.

7. The LED chip according to claim 4 , wherein the first electrode of the at least one first electrode is arranged around the plurality of epitaxial structures.

8. The LED chip according to claim 1 , wherein the plurality of epitaxial structures are arranged in an array.

9. The LED chip according to claim 8 , wherein a plurality of second semiconductor patterns in the plurality of epitaxial structures are arranged in an array.

10. The LED chip according to claim 9 , wherein a plurality of light-emitting patterns in the plurality of epitaxial structures are arranged in an array.

11. The LED chip according to claim 8 , wherein the first electrode of the at least one first electrode is located in the gap between at least two adjacent epitaxial structures in the plurality of epitaxial structures; and
the first electrode of the at least one first electrode includes at least one first portion extending along a first direction and at least one second portion extending along a second direction, wherein the first direction intersects the second direction.

12. The LED chip according to claim 1 , wherein a dimension of the gap between any two adjacent epitaxial structures of the plurality of epitaxial structures ranges from 0.01 μm to 100 μm.

13. The LED chip according to claim 1 , further comprising:
at least one first conductive pin, the at least one first conductive pin being located on a side of the at least one first electrode away from the first semiconductor layer and being electrically connected to the at least one first electrode; and
a plurality of second conductive pins, each second conductive pin being electrically connected to a respective second electrode of the plurality of second electrodes.

14. The LED chip according to claim 1 , further comprising: an ohmic contact layer provided between the second semiconductor pattern and the second electrode electrically connected thereto.

15. The LED chip according to claim 14 , wherein the ohmic contact layer is a transparent ohmic contact layer or a reflective ohmic contact layer.

16. A method for manufacturing a light emitting diode (LED) chip, comprising:
providing a substrate;
forming a plurality of epitaxial structures on a side of the substrate, any two adjacent epitaxial structures of the plurality of epitaxial structures having a gap therebetween, each epitaxial structure including a first semiconductor pattern, a light-emitting pattern and a second semiconductor pattern stacked in sequence, and first semiconductor patterns in at least two of the plurality of epitaxial structures being connected to each other to form a first semiconductor layer;
forming at least one first electrode, a first electrode of the at least one first electrode being electrically connected to a respective first semiconductor layer, wherein the second semiconductor pattern is disposed independently, an orthographic projection of the first electrode of the at least one first electrode on a first plane is located within an orthographic projection of the respective first semiconductor layer electrically connected to the first electrode of the at least one first electrode on the first plane, and does not overlap with orthographic projections of the plurality of epitaxial structures on the first plane, the first plane being a plane parallel to the first semiconductor layer; and
forming a plurality of second electrodes, each second electrode being electrically connected to the second semiconductor pattern in at least one of the plurality of epitaxial structures.

17. The method according to claim 16 , wherein forming the plurality of epitaxial structures, includes:
forming a first semiconductor film, a light-emitting film and a second semiconductor film on the side of the substrate in sequence;
forming a conductive film on a side of the second semiconductor film away from the substrate;
annealing the conductive film to form a plurality of conductive particles; and
patterning the second semiconductor film, the light-emitting film and the first semiconductor film to form first semiconductor patterns, light-emitting patterns and second semiconductor patterns by using the plurality of conductive particles as a mask, so as to obtain the plurality of epitaxial structures.

18. The method according to claim 16 , wherein forming the plurality of epitaxial structures, includes:
forming a first semiconductor film on the side of the substrate;
forming a defining layer on the first semiconductor film away from the substrate, the defining layer having a plurality of openings; and
forming a light-emitting pattern and a second semiconductor pattern in each opening in sequence, so as to obtain the plurality of epitaxial structures; or
forming the plurality of epitaxial structures, includes:
forming a first semiconductor film and a light-emitting film on the side of the substrate in sequence;
forming a defin

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Mingxing
• Tong Binbin
• Zhang Lizhen
• Zhang Chenyang
• Zhang Zhen
• Yun Xiawei
• Yuan Guangcai
• Dong Xue
• Di Muxin
• Liang Zhiwei
• Wang Ke
• Cao Zhanfeng

Classifications

• H10W90/00

  Package configurations · CPC title

• H10H20/0364

  of interconnections · CPC title

• H10H20/032

  of electrodes · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/841

  Reflective coatings, e.g. dielectric Bragg reflectors · CPC title