Display substrate, method of forming the same, display panel and display device including sub-channel portions

Patent metadata

Field	Value
Publication number	US-12021087-B2
Application number	US-201917255815-A
Country	US
Kind code	B2
Filing date	Oct 22, 2019
Priority date	Oct 22, 2019
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

A display substrate, a method of forming a display substrate, a display panel and a display device are provided. The display substrate includes a thin film transistor array layer, where a semiconductor material layer pattern of a driving transistor in the thin film transistor array layer includes a first channel portion, and the first channel portion includes a first sub-channel portion and a second sub-channel portion; the semiconductor material layer pattern further includes a first conductive portion, an included angle between a straight line where a current conduction direction of the first sub-channel portion is located and a straight line where an extending direction of a data line in the thin film transistor array layer is located is a first included angle.

First claim

What is claimed is:

1. A display substrate, comprising a base substrate and a thin film transistor array layer arranged on the base substrate, wherein
a semiconductor material layer pattern of a driving transistor in the thin film transistor array layer comprises a first channel portion, and the first channel portion comprises a first sub-channel portion and a second sub-channel portion;
the semiconductor material layer pattern further comprises a first conductive portion connected to the first sub-channel portion;
an included angle between a straight line where a current conduction direction of the first sub-channel portion is located and a straight line where an extending direction of a data line in the thin film transistor array layer is located is a first included angle;
an included angle between a straight line where a current conduction direction of the second sub-channel portion is located and the straight line where the extending direction of the data line is located is a second included angle;
an included angle between a straight line where a current conduction direction of the first conductive portion is located and the straight line where the extending direction of the data line is located is a third included angle;
the first included angle is smaller than the second included angle, and the third included angle is smaller than the second included angle;
wherein the second sub-channel portion comprises a first horizontal channel portion and a second horizontal channel portion, and both the first horizontal channel portion and the second horizontal channel portion are zigzag.

2. The display substrate according to claim 1 , wherein a length of the first sub-channel portion is greater than a length of the second sub-channel portion.

3. The display substrate according to claim 1 , wherein the first channel portion is a portion where the semiconductor material layer pattern of the driving transistor overlaps with a gate electrode of the driving transistor.

4. The display substrate according to claim 1 , wherein the first channel portion is a zigzag channel portion.

5. The display substrate according to claim 4 , wherein the current conduction direction of the first sub-channel portion is substantially parallel to the extending direction of the data line, and the current conduction direction of the second sub-channel portion is substantially perpendicular to the extending direction of the data line.

6. The display substrate according to claim 1 , wherein a ratio of a length of the first sub-channel portion to a total length of the first channel portion is greater than 0.5.

7. The display substrate according to claim 4 , wherein the semiconductor material layer pattern of the driving transistor further comprises a second conductive portion, the first conductive portion and the second conductive portion are arranged on opposite sides of the first channel portion;
the first sub-channel portion comprises a first vertical channel portion, a second vertical channel portion and a third vertical channel portion, wherein
a first end of the first vertical channel portion is connected to the first conductive portion, a second end of the first vertical channel portion is connected to a first end of the first horizontal channel portion, a second end of the first horizontal channel portion is connected to a first end of the second vertical channel portion, a second end of the second vertical channel portion is connected to a first end of the second horizontal channel portion, a second end of the second horizontal channel portion is connected to a first end of the third vertical channel portion, and a second end of the third vertical channel portion is connected to the second conductive portion.

8. The display substrate according to claim 7 , wherein the semiconductor material layer pattern further comprises a first horizontal conductive portion and a first vertical conductive portion;
a first end of the first conductive portion is connected to the first end of the first vertical channel portion;
a first end of the first horizontal conductive portion is connected to a second end of the first conductive portion, and a second end of the first horizontal conductive portion is connected to the first vertical conductive portion.

9. The display substrate according to claim 8 , wherein a length of the first vertical conductive portion is greater than a length of the first horizontal conductive portion, the length of the first vertical conductive portion is greater than a length of the first conductive portion.

10. The display substrate according to claim 7 , wherein the semiconductor material layer pattern further comprises a second horizontal conductive portion and a second vertical conductive portion;
a first end of the second conductive portion is connected to the second end of the third vertical channel portion;
a first end of the second horizontal conductive portion is connected to a second end of the second conductive portion, and a second end of the second horizontal conductive portion is connected to the second vertical conductive portion.

11. The display substrate according to claim 10 , wherein a length of the second vertical conductive portion is greater than a length of the second horizontal conductive portion, the length of the second vertical conductive portion is greater than a length of the second conductive portion.

12. The display substrate according to claim 7 , wherein an area of an orthographic projection of the second conductive portion on the substrate is greater than an area of an orthographic projection of the first conductive portion on the substrate.

13. The display substrate according to claim 1 , wherein the thin film transistor array layer comprises a first gate metal layer and a semiconductor material layer, the first gate metal layer comprises a gate electrode of the driving transistor, a gate line at a first side of the gate electrode and a light-emitting control signal line at a second side of the gate electrode;
an orthographic projection of the gate line on the substrate, an orthographic projection of the light-emitting control signal line on the substrate and an orthographic projection of the semiconductor material layer on the substrate forms a rectangular region;
a length of the rectangular area is greater than a width of the rectangular area;
the width of the rectangular region is the width of the rectangular region along a direction of the gate line, and the length of the rectangular region is the length of the rectangular region along a direction perpendicular to the gate line.

14. The display substrate according to claim 7 , wherein the thin film transistor array layer comprises a light-emitting control transistor;
a channel portion of a semiconductor material layer pattern of the light-emitting control transistor, the second conductive portion, the first channel portion and the first conductive portion are sequentially arranged along a longitudinal direction.

15. The display substrate according to claim 14 , wherein the thin film transistor array layer comprises a first light-emitting control transistor and a second light-emitting control transistor;
a semiconductor material layer pattern of the first light-emitting control transistor comprises a second channel portion, the semiconductor material layer pattern of the second light-emitting control transistor comprises a third channel portion;
the second channel portion, the second conductive portion, the first channel portion and the first conductive portion are sequentially arranged along the longitudinal direction;
the third

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Diao Yongfu
• Wang Wenkang
• Yang Zhongliu
• Chen Chenyu

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0223

  comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials · CPC title

• H10D86/421 Primary

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title