Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-12020935-B2
Application number	US-202117563603-A
Country	US
Kind code	B2
Filing date	Dec 28, 2021
Priority date	Mar 25, 2021
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

An object of the present disclosure is to reduce masks and to reduce the variation in the profile of an impurity layer in a semiconductor device. A method of manufacturing a semiconductor device includes a step (b) of forming a base layer on a first main surface side of a drift layer in an active region by implanting p-type impurity ions of using the first mask, a step of (c) of forming an emitter layer on the first main surface side of the base layer by implanting n-type impurity ions using the first mask, a step (d) of forming trenches after the steps (b) and (c), a step (e) of embedding a gate electrode inside the trenches, and a step (g) of converting a part of the emitter layer into a first contact layer by implanting the p-type impurity ions having a high dosage using a second mask.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device demarcated into an active region, a boundary region surrounding the active region, and an edge region surrounding the boundary region in plan view, the method comprising:
a step (a) of forming a first mask on a first main surface of the semiconductor substrate having a drift layer of a first conductivity type;
a step (b) of forming a base layer of a second conductivity type on a side of the first main surface of at least a part a region of the drift layer in the active region by implanting impurity ions of the second conductivity type into the first main surface of the semiconductor substrate using the first mask;
a step of (c) of forming an impurity layer of the first conductivity type on the side of the first main surface of the base layer by implanting impurity ions of the first conductivity type into the first main surface of the semiconductor substrate using the first mask;
a step (d) of forming trenches reaching the drift layer from the first main surface of the semiconductor substrate after the steps (b) and (c);
a step (e) of embedding a gate electrode inside the trenches via a gate insulating film;
a step (f) of forming a second mask having a different pattern from that of the first mask on the first main surface of the semiconductor substrate; and
a step (g) of converting a part of the impurity layer into a first contact layer of the second conductivity type by implanting impurity ions of the second conductivity type having a dosage higher than that of the impurity ions of the first conductivity type implanted at the step (c) into the first main surface of the semiconductor substrate using the second mask.

2. The method of manufacturing the semiconductor device according to claim 1 , further comprising
a step (h) of forming a well layer of the second conductivity type in the semiconductor substrate in the boundary region and the edge region, wherein
the step (g) is a step of forming a second contact layer of the second conductivity type on the side of the first main surface of the well layer in the boundary region at a same time as when converting a part of the impurity layer into the first contact layer, and
a net impurity concentration of the second contact layer is higher than a net impurity concentration of the first contact layer.

3. The method of manufacturing the semiconductor device according to claim 1 , wherein
a diffusion coefficient of the impurity ions of the second conductivity type implanted at the step (b) in the semiconductor substrate is greater than a diffusion coefficient of the impurity ions of the first conductivity type implanted at the step (c) in the semiconductor substrate.

4. The method of manufacturing the semiconductor device according to claim 1 , wherein
a width of the boundary region is greater than a depth of the impurity layer.

5. The method of manufacturing the semiconductor device according to claim 1 , wherein
a depth of the first contact layer is greater than a depth of the impurity layer.

6. The method of manufacturing the semiconductor device according to claim 1 , wherein
the step (g) is a step of forming a third contact layer of the second conductivity type in the drift layer in contact with the first main surface of the semiconductor substrate in the active region at a same time as when converting the part of the impurity layer into the first contact layer,
the third contact layer does not contain impurities of the first conductivity type having a concentration higher than a concentration of impurities of the first conductivity type of the drift layer, and
a net impurity concentration of the third contact layer is higher than the net impurity concentration of the first contact layer.

7. A method of manufacturing a semiconductor device demarcated into an active region, a boundary region surrounding the active region, and an edge region surrounding the boundary region in plan view, the method comprising:
a step (a) of forming a first mask on a first main surface of the semiconductor substrate having a drift layer of a first conductivity type;
a step (b) of forming a base layer of a second conductivity type on a side of the first main surface of the drift layer in the active region by implanting impurity ions of the second conductivity type into the first main surface of the semiconductor substrate using the first mask;
a step of (c) of forming a contact layer of the second conductivity type on the side of the first main surface of the base layer by implanting impurity ions of the second conductivity type into the first main surface of the semiconductor substrate using the first mask;
a step (d) of forming trenches reaching the drift layer from the first main surface of the semiconductor substrate after the steps (b) and (c);
a step (e) of embedding a gate electrode inside the trenches via a gate insulating film;
a step (f) of forming a second mask having a different pattern from that of the first mask on the first main surface of the semiconductor substrate; and
a step (g) of converting a part of the contact layer into an impurity layer of the first conductivity type by implanting impurity ions of the first conductivity type having a dosage higher than that of the impurity ions of the second conductivity type implanted at the step (c) into the first main surface of the semiconductor substrate using the second mask.

8. The method of manufacturing the semiconductor device according to claim 7 , further comprising
a step (h) of forming a first well layer of the second conductivity type in the semiconductor substrate in the boundary region and the edge region, wherein
the step (b) is a step of forming a second well layer of the second conductivity type on the side of the first main surface of the first well layer in the boundary region at a same time as when forming the base layer, and
a net impurity concentration of the second well layer is higher than a net impurity concentration of the first well layer.

Assignees

• Mitsubishi Electric Corp

Inventors

• Nishi Koichi
• Soneda Shinya
• Konishi Kazuya

Classifications

• H10P32/19

  Diffusion sources · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10P30/22 Primary

  using masks · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/1406

  by ion implantation · CPC title