Image output device and image output method

Patent metadata

Field	Value
Publication number	US-12020668-B2
Application number	US-202117525981-A
Country	US
Kind code	B2
Filing date	Nov 15, 2021
Priority date	Nov 25, 2020
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

An image output device coupled to a first and second signal source and a method thereof. The image output device includes memories configured to store frame image data respectively, a source selection circuit coupled to the first and second signal sources and the memories and configured to choose to store a first frame image data transmitted by the first or second signal source in one of the memories according to a working state of the first signal source, and an image output circuit coupled to the memories and the source selection circuit and configured to output the first frame image data stored in one of the memories. The image output device may rapidly switch to a backup signal source when the signal source is unstable to achieve fast switching and perfect connection.

First claim

What is claimed is:

1. An image output device, wherein the image output device is coupled to a first signal source and a second signal source, and the image output device comprises:
a plurality of memories configured to store a plurality of frame image data respectively;
a source selection circuit coupled to the first signal source, the second signal source, and the plurality of memories, and the source selection circuit is configured to choose a first frame image data transmitted by the first signal source or the first frame image data transmitted by the second signal source according to a working state of the first signal source, wherein one of the plurality of memories stores the first frame image data transmitted by the first signal source or the first frame image data transmitted by the second signal source chosen by the source selection circuit, wherein content of the first frame image data transmitted from the first signal source and content of the first frame image data transmitted from the second signal source are the same, wherein the source selection circuit comprises:
a first pre-processing circuit coupled between the first signal source and the plurality of memories, and the first pre-processing circuit is configured to perform a digital signal processing on the first frame image data from the first signal source to generate a processed first frame image data,
wherein the first pre-processing circuit comprises a first state detection circuit configured to detect whether the working state of the first signal source is abnormal,

wherein the source selection circuit is further configured to determine whether to store the processed first frame image data to one of the plurality of memories according to a detection result; and
an image output circuit coupled to the plurality of memories and the source selection circuit and configured to output the first frame image data stored in corresponding one of the plurality of memories.

2. The image output device of claim 1 , wherein there is a delay of at least one frame time interval between the first frame image data outputted by the image output device and the first frame image data inputted to the image output device.

3. The image output device of claim 1 , wherein the first state detection circuit is configured to sample a pixel clock signal of the first signal source and determine the working state of the first signal source is abnormal when a sampling result is less than a threshold.

4. The image output device of claim 1 , wherein the first frame image data comprises a horizontal synchronizing signal and two consecutive pulses of the horizontal synchronizing signal are separated by a first time interval, and the first state detection circuit is configured to determine the working state of the first signal source is abnormal when a length of the first time interval is greater than a threshold.

5. The image output device of claim 1 , wherein the first pre-processing circuit further comprises:
a first control circuit configured to sequentially designate one of the plurality of memories as a designated memory according to a storage order; and
a first data packing circuit configured to pack the first frame image data and store the packed first frame image data in the designated memory when the working state of the first signal source is normal,
wherein the storage order is determined by the source selection circuit according to a usage status of the plurality of memories.

6. The image output device of claim 1 , wherein the source selection circuit is further configured to choose the first frame image data transmitted by the first signal source or the first frame image data transmitted by the second signal source according to the working state of the first signal source and the working state of the second signal source, wherein
one of the plurality of memories stores the first frame image data transmitted by the first signal source or the first frame image data transmitted by the second signal source chosen by the source selection circuit.

7. The image output device of claim 1 , wherein a number of the plurality of memories is three, and when the first frame image data stored in one of the memories is outputted, the source selection circuit designates one of the memories as a designated memory to store a second frame image data transmitted by the first signal source or the second frame image data transmitted by the second signal source, wherein the second frame image data is immediately after the first frame image data in a display timing.

8. The image output device of claim 1 , wherein a number of the plurality of memories is three, and an output order of the frame image data in the three memories is first in, first out.

9. The image output device of claim 1 , wherein the image output circuit further comprises:
a first post-processing circuit coupled to the plurality of memories and configured to perform a digital signal processing on a frame image data read from a designated memory, wherein the first post-processing circuit comprises:
a third control circuit configured to generate a read control signal according to the control signal generated from the source selection circuit and transmit the read control signal to the plurality of memories; and
a data unpack circuit configured to unpack the read frame image data.

10. An image output method suitable for an image output device, wherein the image output device is coupled to a first signal source and a second signal source, the image output device comprises a plurality of memories, and the image output method comprises:
determining a working state of the first signal source by the image output device;
choosing a first frame image data transmitted by the first signal source or the first frame image data transmitted by the second signal source by the image output device according to the working state of the first signal source, wherein a first memory in the plurality of memories stores the first frame image data transmitted by the first signal source or the first frame image data transmitted by the second signal source chosen by the image output device, wherein content of the first frame image data transmitted from the first signal source and content of the first frame image data transmitted from the second signal source are the same;
performing a digital signal processing on the first frame image data transmitted by the first signal source to generate a processed first frame image data by the image output device;
detecting whether the working state of the first signal source is abnormal, and determining whether to store the processed first frame image data to the first memory according to a detection result by the image output device; and
outputting the first frame image data from the first memory by the image output device.

11. The image output method of claim 10 , wherein there is a delay of at least one frame time interval between the first frame image data outputted by the image output device and the first frame image data inputted to the image output device.

12. The image output method of claim 10 , further comprising:
sampling a pixel clock signal of the first signal source and determining the working state of the first signal source is abnormal when a sampling result is less than a threshold.

13. The image output method of claim 10 , wherein the first frame image data comprises a horizontal synchronizing signal, two consecutive pulses of the horizontal synchronizing signal are separated by a first time interval, and the image output method further comprises:
detecting a length of the first time interval, and determining the working stat

Assignees

• Coretronic Corp

Inventors

• Chang Keng-Chia
• Wang Fu-Shan
• Chen Li-Ming

Classifications

• G09G2370/20

  Details of the management of multiple sources of image data · CPC title

• G09G2360/12

  Frame memory handling · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G5/393 Primary

  Arrangements for updating the contents of the bit-mapped memory · CPC title

• G09G5/006

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title