Apparatuses and methods including memory commands for semiconductor memories

Patent metadata

Field	Value
Publication number	US-12019570-B2
Application number	US-202318149817-A
Country	US
Kind code	B2
Filing date	Jan 4, 2023
Priority date	Nov 29, 2017
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

First claim

What is claimed is:

1. An apparatus, comprising:
a data clock path including an input buffer, the input buffer configured to pass a data clock signal when enabled and the data clock path configured to provide a plurality of internal clock signals based on the data clock signal, the data clock path further including a clock signal synchronization circuit configured to synchronize a first internal clock signal of the plurality of internal clock signals with the data clock signal;
a command input circuit configured to receive access commands and timing commands associated with the access commands, and further configured to provide internal access commands responsive to receiving the access commands, to provide an internal first timing command responsive to receiving a first timing command of the timing commands, and to provide an internal second timing command responsive to receiving a second timing command of the timing commands; and
a command decoder coupled to the command input circuit and configured to decode the internal access commands and provide internal access control signals to perform corresponding access operations and further configured to decode the internal timing command and to enable the input buffer of the data clock path and to control the clock signal synchronization circuit to synchronize the first internal clock signal of the plurality of internal clock signals with the data clock signal at a time based on an opcode included in the timing commands.

2. The apparatus of claim 1 wherein the plurality of internal clock signals comprises multiphase clock signals and wherein the data clock path further includes a clock divider circuit configured to provide the multiphase clock signals based on the data clock signals.

3. The apparatus of claim 1 wherein the command decoder is further configured to activate the input buffer at a time based on the opcode included in the timing command.

4. The apparatus of claim 1 wherein the command input circuit is configured to receive a first part of a timing command responsive to a first clock edge of a clock signal and to receive a second part of the timing command responsive to a second clock edge of the clock signal, wherein a clock signal synchronization option is included in the first part of the timing command and the opcode is included in the second part of the timing command when the clock signal synchronization option is enabled.

5. The apparatus of claim 4 wherein the opcode included in the second part of the timing command corresponds to a number of additional clock cycles of the clock signal of delay before the clock signal synchronization circuit is controlled to begin synchronizing the first internal clock signal of the plurality of internal clock signals with the data clock signal.

6. The apparatus of claim 5 wherein the additional clock cycles of the clock signal are added to a time measured from receipt of the timing command.

7. The apparatus of claim 4 wherein the clock signal synchronization option comprises a fast clock signal synchronization for the data clock signal and the clock signal.

8. The apparatus of claim 4 , wherein the clock signal has a lower frequency than the data clock signal.

9. The apparatus of claim 1 , wherein at least one of the access commands comprises a read command or a write command.

10. The apparatus of claim 1 , wherein at least one of the timing commands comprises a CAS command.

11. A method comprising:
passing, with an input buffer when enabled, a data clock signal to a data clock path;
providing, with the data clock path, a plurality of internal clock signals based on the data clock signal;
synchronizing, with the data clock path, a first internal clock signal of the plurality of internal clock signals with the data clock signal;
receiving, with a command input circuit, access commands and timing commands associated with the access commands;
providing, with the command input circuit, an internal first timing command and an internal second timing command;
decoding, with the command decoder, the first and second internal timing commands; and
enabling, with the command decoder, the input buffer of the data clock path and to control the clock signal synchronization circuit to synchronize the first internal clock signal of the plurality of internal clock signals with the data clock signal at a time based on an opcode included in the timing commands.

12. The method of claim 11 , further comprising:
decoding with the command decoder, the internal access commands; and
providing internal access control signals to perform corresponding access operations.

13. The method of claim 11 , wherein a timing command of the timing commands comprises a CAS command.

14. The method of claim 11 , wherein an access command of the access commands comprises a read or a write command.

15. The method of claim 11 , wherein the first and second internal timing commands are provided responsive to a first timing command and a second timing command of the timing commands, respectively.

16. The method of claim 11 , wherein the plurality of internal clock signals comprises multiphase clock signals, and the method further comprises providing, with a clock divider circuit, the multiphase clock signals based on the data clock signals.

17. The method of claim 11 , further comprising:
receiving, with the command input circuit, a first part of a timing command responsive to a first clock edge of a clock signal;
receiving, with the command input circuit, a second part of the timing command responsive to a second clock edge of the clock signal.

18. The method of claim 17 , wherein a clock synchronization option is included in the first part of the timing command and the opcode is included in the second part of the timing command when the clock signal synchronization option is enabled.

19. The method of claim 18 , wherein the opcode included in the second part of the timing command corresponds to a number of additional clock cycles of the clock signal of delay before the clock signal synchronization circuit is controlled to begin synchronizing the first internal clock signal of the plurality of internal clock signals with the data clock signal.

20. The method of claim 18 , wherein the clock signal synchronization option comprises a fast clock signal synchronization for the data clock signal and the clock signal.

Assignees

• Micron Technology Inc

Inventors

• Kim Kang-Yong
• Gans Dean

Classifications

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title