Fin cut and fin trim isolation for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-12016170-B2
Application number	US-202318124936-A
Country	US
Kind code	B2
Filing date	Mar 22, 2023
Priority date	Nov 30, 2017
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a discrete three-dimensional body comprising silicon, the discrete three-dimensional body having a channel region, and the discrete three-dimensional body having a longest dimension along a first direction;
an isolation structure separating a first end of a first portion of the discrete three-dimensional body from a first end of a second portion of the discrete three-dimensional body along the first direction, the isolation structure having a width along the first direction, wherein the isolation structure is on a portion of the first portion of the discrete three-dimensional body;
a first gate structure completely surrounding the channel region of the first portion of the discrete three-dimensional body, wherein the first gate structure has the width along the first direction, and wherein a center of the first gate structure is spaced apart from a center of the isolation structure by a pitch along the first direction; and
a second gate structure over a second end of the first portion of the discrete three-dimensional body, the second end opposite the first end, the second gate structure having the width along the first direction, wherein a center of the second gate structure is spaced apart from the center of the gate first structure by the pitch along the first direction, wherein the second gate structure is completely surrounding a portion of the first portion of the discrete three-dimensional body.

2. The integrated circuit structure of claim 1 , wherein the first gate structure and the second gate structure comprise a same conductive material.

3. The integrated circuit structure of claim 1 , wherein the first end of the first portion of the discrete three-dimensional body has a surface roughness, and the second end of the first portion of the discrete three-dimensional body has a surface roughness less than the surface roughness of the first end of the first portion of the discrete three-dimensional body.

4. The integrated circuit structure of claim 1 , wherein the first end of the first portion of the discrete three-dimensional body has a scalloped topography.

5. The integrated circuit structure of claim 1 , further comprising:
a first epitaxial semiconductor region on the first portion of the discrete three-dimensional body between the first gate structure and the isolation structure; and
a second epitaxial semiconductor region on the first portion of the discrete three-dimensional body between the first gate structure and the second gate structure.

6. The integrated circuit structure of claim 5 , wherein the first and second epitaxial semiconductor regions each have a width along a second direction orthogonal to the first direction, the width along the second direction wider than a width of the first portion of the discrete three-dimensional body along the second direction beneath the first gate structure.

7. The integrated circuit structure of claim 1 , the first gate structure and the second gate structure each comprising a high-k dielectric layer between a gate electrode and the first portion of the discrete three-dimensional body, the high-k dielectric layer along sidewalls of the gate electrode.

8. An integrated circuit structure, comprising:
a discrete three-dimensional body comprising silicon, the discrete three-dimensional body having a channel region, and the discrete three-dimensional body having a longest dimension along a first direction;
an isolation structure separating a first end of a first portion of the discrete three-dimensional body from a first end of a second portion of the discrete three-dimensional body along the first direction, the isolation structure having a width along the first direction, the first end of the first portion of the discrete three-dimensional body having a surface roughness;
a gate structure comprising a gate electrode completely surrounding the channel region of the first portion of the discrete three-dimensional body, wherein the gate structure has the width along the first direction, and wherein a center of the gate structure is spaced apart from a center of the isolation structure by a pitch along the first direction; and
a dummy gate structure over a second end of the first portion of the discrete three-dimensional body, the second end opposite the first end, the dummy gate structure having the width along the first direction, wherein a center of the dummy gate structure is spaced apart from the center of the gate structure by the pitch along the first direction, wherein the second end of the first portion of the discrete three-dimensional body has a surface roughness less than the surface roughness of the first end of the first portion of the discrete three-dimensional body.

9. The integrated circuit structure of claim 8 , wherein the first end of the first portion of the discrete three-dimensional body has a scalloped topography.

10. The integrated circuit structure of claim 8 , further comprising:
a first epitaxial semiconductor region on the first portion of the discrete three-dimensional body between the gate structure and the isolation structure; and
a second epitaxial semiconductor region on the first portion of the discrete three-dimensional body between the gate structure and the dummy gate structure.

11. The integrated circuit structure of claim 10 , wherein the first and second epitaxial semiconductor regions have a width along a second direction orthogonal to the first direction, the width along the second direction wider than a width of the first portion of the discrete three-dimensional body along the second direction beneath the gate structure.

12. The integrated circuit structure of claim 8 , the gate structure further comprising a high-k dielectric layer between the gate electrode and the first portion of the discrete three-dimensional body and along sidewalls of the gate electrode.

13. An integrated circuit structure, comprising:
a discrete three-dimensional body comprising silicon, the discrete three-dimensional body having a channel region, and the discrete three-dimensional body having a longest dimension along a first direction;
an isolation structure separating a first end of a first portion of the discrete three-dimensional body from a first end of a second portion of the discrete three-dimensional body along the first direction, the isolation structure having a width along the first direction, the first end of the first portion of the discrete three-dimensional body having a surface roughness;
a gate structure comprising a gate electrode completely surrounding the channel region of the first portion of the discrete three-dimensional body, wherein the gate structure has the width along the first direction, and wherein a center of the gate structure is spaced apart from a center of the isolation structure by a pitch along the first direction; and
a dummy gate structure over a second end of the first portion of the discrete three-dimensional body, the second end opposite the first end, the dummy gate structure having the width along the first direction, wherein a center of the dummy gate structure is spaced apart from the center of the gate structure by the pitch along the first direction, wherein the dummy gate structure has a composition different than a composition of the gate structure.

14. The integrated circuit structure of claim 13 , wherein the dummy gate structure comprises polycrystalline silicon.

15. The integrated circuit structure of claim 13 , wherein the dummy gate structure comprises a silicon nitride pillar.

16. The integrated circ

Assignees

• Intel Corp

Inventors

• Ghani Tahir
• Ho Byron
• Ward Curtis W
• Hattendorf Michael L
• Auth Christopher P

Classifications

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/6213

  having rounded corners · CPC title