Digital phase shifter

Patent metadata

Field	Value
Publication number	US-12015387-B2
Application number	US-202318101623-A
Country	US
Kind code	B2
Filing date	Jan 26, 2023
Priority date	Jun 27, 2022
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A digital phase shifter includes a plurality of digital phase shift circuit groups in which a plurality of digital phase shift circuits are connected in cascade and one or more bend-type connection units connected between two digital phase shift circuit groups. At least one of the digital phase shift circuits constituting at least one digital phase circuit group is a mitigation circuit that mitigates a distribution of phase shift amounts.

First claim

What is claimed is:

1. A digital phase shifter comprising:
a plurality of digital phase shift circuit groups in which a plurality of digital phase shift circuits are connected in cascade; and
one or more bend-type connection units connected between two digital phase shift circuit groups,
wherein each of the digital phase shift circuits includes at least a signal line, a pair of inner lines provided at both sides of the signal line, a pair of outer lines provided outside of the inner lines, a first ground conductor connected to one end of each of the inner lines and the outer lines, a second ground conductor connected to the other end of each of the outer lines, a pair of electronic switches provided between the other ends of the inner line and the second ground conductor, and a capacitor electrically connected between the signal line and at least one of the first ground conductor and the second ground conductor,
wherein each of the digital phase shift circuits is a circuit set in a low-delay mode in which a return current flows through the inner line or a high-delay mode in which a return current flows through the outer line, and
wherein at least one of the digital phase shift circuits constituting at least one digital phase shift circuit group is a mitigation circuit configured to mitigate a distribution of phase shift amounts.

2. The digital phase shifter according to claim 1 , wherein the mitigation circuit includes at least one of:
a first mitigation circuit that is the digital phase shift circuit having a larger phase shift amount than the digital phase shift circuit other than the mitigation circuit and that is configured to mitigate a recess portion in the distribution of phase shift amounts; and
a second mitigation circuit that is the digital phase shift circuit having a smaller phase shift amount than the digital phase shift circuit other than the mitigation circuit and that is configured to mitigate a projection portion in the distribution of phase shift amounts.

3. The digital phase shifter according to claim 2 , wherein at least one of the digital phase shift circuits constituting at least one digital phase shift circuit group having both ends connected to the connection unit is the first mitigation circuit.

4. The digital phase shifter according to claim 2 , wherein a control of whether to set the mode as the low-delay mode or the high-delay mode in the digital phase shift circuit is started from the digital phase shift circuit which is located at a side in which the capacitor is provided between two digital phase shift circuits located at an outermost side and is sequentially performed in a connection order of the digital phase shift circuits.

5. The digital phase shifter according to claim 4 , wherein at least one digital phase shift circuit located behind at least one connection unit in a direction in which the digital phase shift circuit is controlled is the first mitigation circuit.

6. The digital phase shifter according to claim 4 , wherein at least one digital phase shift circuit located in front of at least one connection unit in a direction in which the digital phase shift circuit is controlled is the second mitigation circuit.

7. The digital phase shifter according to claim 2 ,
wherein the first mitigation circuit satisfies at least one of a condition that a length of the first mitigation circuit is longer than that of the digital phase shift circuit other than the mitigation circuit, a condition that a distance between the signal line and the inner line in the first mitigation circuit is shorter than that in the digital phase shift circuit other than the mitigation circuit, a condition that a distance between the signal line and the outer line in the first mitigation circuit is longer than that in the digital phase shift circuit other than the mitigation circuit, a condition that the capacitor of the first mitigation circuit is larger than that of the digital phase shift circuit other than the mitigation circuit, and a condition that the pair of electronic switches of the first mitigation circuit are larger than those of the digital phase shift circuit other than the mitigation circuit, and
wherein the second mitigation circuit satisfies at least one of a condition that a length of the second mitigation circuit is shorter than that of the digital phase shift circuit other than the mitigation circuit, a condition that a distance between the signal line and the inner line in the second mitigation circuit is longer than that in the digital phase shift circuit other than the mitigation circuit, a condition that a distance between the signal line and the outer line in the second mitigation circuit is shorter than that in the digital phase shift circuit other than the mitigation circuit, a condition that the capacitor of the second mitigation circuit is smaller than that of the digital phase shift circuit other than the mitigation circuit, and a condition that the pair of electronic switches of the second mitigation circuit are smaller than those of the digital phase shift circuit other than the mitigation circuit.

8. The digital phase shifter according to claim 1 , wherein the digital phase shift circuit includes an electronic switch configured to switch between whether or not to connect the capacitor between the signal line and at least one of the first ground conductor and the second ground conductor.

9. The digital phase shifter according to claim 1 , wherein the connection unit includes:
a first connection line configured to connect the signal lines of the digital phase shift circuits located at ends of two digital phase shift circuit groups;
a second connection line configured to connect the inner lines of the digital phase shift circuits located at ends of two digital phase shift circuit groups;
a ground layer arranged in at least one of an upward direction and a downward direction of the first connection line and the second connection line; and
a via-hole configured to connect at least the second connection line and the ground layer.

10. The digital phase shifter according to claim 9 , wherein the connection unit includes a third connection line configured to connect the outer lines of the digital phase shift circuits located at outermost ends of two digital phase shift circuit groups.

Assignees

• Fujikura Ltd

Inventors

• Uemichi Yusuke

Classifications

• H03H11/16

  Networks for phase shifting · CPC title

• H01P1/185

  using a diode or a gas filled discharge tube · CPC title

• H03H17/08 Primary

  Networks for phase shifting · CPC title

• H01P1/184 Primary

  Strip line phase-shifters (H01P1/181, H01P1/185, H01P1/19 take precedence) · CPC title